Yuko Hara-Azumi
Orcid: 0000-0001-9486-5272
According to our database1,
Yuko Hara-Azumi
authored at least 83 papers
between 2006 and 2024.
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Bibliography
2024
Hardware/Software Codesign of Real-Time Intrusion Detection System for Internet of Things Devices.
IEEE Internet Things J., June, 2024
Hardware/Software Cooperative Design Against Power Side-Channel Attacks on IoT Devices.
IEEE Internet Things J., May, 2024
Mixed-Precision Neural Architecture Search and Dynamic Split Point Selection for Split Computing.
IEEE Access, 2024
A Comparative Study of Loss Functions for Arbitrary-Oriented Object Detection in Aerial Images.
Proceedings of the 21st International Joint Conference on Computer Science and Software Engineering, 2024
High-Level Synthesis Countermeasure Using Threshold Implementation with Mixed Number of Shares.
Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2024
Proceedings of the 21st IEEE Consumer Communications & Networking Conference, 2024
2023
Power Side-channel Attack Resistant Circuit Designs of ARX Ciphers Using High-level Synthesis.
ACM Trans. Embed. Comput. Syst., September, 2023
J. Inf. Process., 2023
Implementation of Deep Joint Source-Channel Coding on 5G Systems for Image Transmission.
Proceedings of the 98th IEEE Vehicular Technology Conference, 2023
Dynamic Split Computing-Aware Mixed-Precision Quantization for Efficient Deep Edge Intelligence.
Proceedings of the 22nd IEEE International Conference on Trust, 2023
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023
Convergence Improvement by Parameters Exchange in Asynchronous Decentralized Federated Learning for Non-IID Data.
Proceedings of the 49th Euromicro Conference on Software Engineering and Advanced Applications, 2023
Impact of Quantization Noise on CNN-based Joint Source-Channel Coding and Modulation.
Proceedings of the 20th IEEE Consumer Communications & Networking Conference, 2023
Proceedings of the Eleventh International Symposium on Computing and Networking, CANDAR 2023, 2023
2022
Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications.
ACM Trans. Design Autom. Electr. Syst., 2022
Real-Time Resource Allocation in Passive Optical Network for Energy-Efficient Inference at GPU-Based Network Edge.
IEEE Internet Things J., 2022
Multimodal Neural Network Acceleration on a Hybrid CPU-FPGA Architecture: A Case Study.
IEEE Access, 2022
Proceedings of the 95th IEEE Vehicular Technology Conference, 2022
Proceedings of the 95th IEEE Vehicular Technology Conference, 2022
Gossip Swap SGD: Lightweight Decentralized Machine Learning for Non-Homogeneous Data Distribution.
Proceedings of the New Trends in Intelligent Software Methodologies, Tools and Techniques, 2022
Examining Vulnerability of HLS-designed Chaskey-12 Circuits to Power Side-Channel Attacks.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Optimized Software Implementations of Ascon, Grain-128AEAD, and TinyJambu on ARM Cortex-M0.
Proceedings of the 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022, 2022
Proceedings of the IEEE Global Communications Conference, 2022
Proceedings of the International Conference on Field-Programmable Technology, 2022
2021
Real-Time Reconfiguration of Time-Aware Shaper for ULL Transmission in Dynamic Conditions.
IEEE Access, 2021
Space- Time- Domain Adaptive Equalizer Employed Successive Interference Cancellation for Underwater Acoustic Communication.
Proceedings of the 94th IEEE Vehicular Technology Conference, 2021
Proceedings of the 13th International Conference on Knowledge and Smart Technology, 2021
Deep Joint Source-Channel Coding and Modulation for Underwater Acoustic Communication.
Proceedings of the IEEE Global Communications Conference, 2021
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic Computing.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Revisiting System Noise in Side-Channel Attacks: Mutual Assistant SCA vs. Genetic Algorithm.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021
2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Revisiting Simple and Energy Efficient Embedded Processor Designs Toward the Edge Computing.
IEEE Embed. Syst. Lett., 2020
Implementation of Lightweight eHealth Applications on a Low-Power Embedded Processor.
IEEE Access, 2020
IEEE Access, 2020
APNAS: Accuracy-and-Performance-Aware Neural Architecture Search for Neural Hardware Accelerators.
IEEE Access, 2020
Proceedings of the 91st IEEE Vehicular Technology Conference, 2020
2019
ACM Trans. Design Autom. Electr. Syst., 2019
ACM Trans. Design Autom. Electr. Syst., 2019
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
Proceedings of the International Conference on Field-Programmable Technology, 2019
Proceedings of the 10th ACM/IEEE International Conference on Cyber-Physical Systems, 2019
2018
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018
2017
A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
IEEE Embed. Syst. Lett., 2017
One-instruction set computer-based multicore processors for energy-efficient streaming data processing.
Proceedings of the International Symposium on Rapid System Prototyping, 2017
Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, 2017
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017
2016
Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Timing speculation-aware instruction set extension for resource-constrained embedded systems.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015
2014
Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs.
IPSJ Trans. Syst. LSI Des. Methodol., 2014
Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-Core SoCs.
IEICE Trans. Inf. Syst., 2014
Differing effects of attention in single-units and populations are well predicted by heterogeneous tuning and the normalization model of attention.
Frontiers Comput. Neurosci., 2014
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks.
IPSJ Trans. Syst. LSI Des. Methodol., 2013
IEICE Trans. Inf. Syst., 2013
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
IEICE Trans. Inf. Syst., 2013
Cost-efficient scheduling in high-level synthesis for Soft-Error Vulnerability Mitigation.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012
Proceedings of the CLEF 2012 Evaluation Labs and Workshop, 2012
Clock-constrained simultaneous allocation and binding for multiplexer optimization in high-level synthesis.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
2009
Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis.
J. Inf. Process., 2009
2008
IPSJ Trans. Syst. LSI Des. Methodol., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study.
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007
Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
2006
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006