Yukiya Miura

According to our database, Yukiya Miura authored at least 56 papers between 1987 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Cooperative Autonomous Driving Control among Vehicles of Different Sizes Using Deep Reinforcement Learning.

Akito Takenaka, Tomohiro Harada, Yukiya Miura, Kiyohiko Hattori, Johei Matuoka

Proceedings of the International Joint Conference on Neural Networks, 2024

Analysis of the Impact of Prediction Accuracy on Search Performance in Surrogate-assisted Evolutionary Algorithms.

Yuki Hanawa, Tomohiro Harada, Yukiya Miura

Proceedings of the IEEE Congress on Evolutionary Computation, 2024

2023

Emergence of Cooperative Automated Driving Control at Roundabouts Using Deep Reinforcement Learning.

Reo Nakaya, Tomohiro Harada, Yukiya Miura, Kiyohiko Hattori, Johei Matsuoka

Proceedings of the 62nd Annual Conference of the Society of Instrument and Control Engineers, 2023

Hybrid Rocket Engine Design Using Pairwise Ranking Surrogate-assisted Differential Evolution.

Hitomi Kano, Tomohiro Harada, Yukiya Miura, Masahiro Kanazaki

Proceedings of the Companion Proceedings of the Conference on Genetic and Evolutionary Computation, 2023

2022

Differential Evolution Using Surrogate Model Based on Pairwise Ranking Estimation for Constrained Optimization Problems.

Hitomi Kano, Tomohiro Harada, Yukiya Miura

Proceedings of the Joint 12th International Conference on Soft Computing and Intelligent Systems and 23rd International Symposium on Advanced Intelligent Systems, 2022

Improving Data Sampling Efficiency of Sensitivity Analysis Based on Bilevel Multi-objective Evolutionary Algorithm.

Takuya Hakoishi, Tomohiro Harada, Yukiya Miura

Proceedings of the Joint 12th International Conference on Soft Computing and Intelligent Systems and 23rd International Symposium on Advanced Intelligent Systems, 2022

2021

A Method for Measuring Process Variations in the FPGA Chip Considering the Effect of Wire Delay.

Yukiya Miura, Shingo Tsutsumi

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

2020

Innovative Test Practices in Asia.

Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, Harry H. Chen, Haruo Kobayashi, Kazumi Hatayama

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test.

Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yukiya Miura

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Soft Error Tolerance of Power-Supply-Noise Hardened Latches.

Yukiya Miura, Yuya Kinoshita

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

2019

Development of FF Circuits for Measures Against Power Supply Noise.

Yukiya Miura, Miyuki Inoue, Yuya Kinoshita

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2017

Simulation-based analysis of FF behavior in presence of power supply noise.

Yukiya Miura, Takuya Yamamoto

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016

Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor.

Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

LSI aging estimation using ring oscillators.

Yukiya Miura, Tatsunori Ikeda

Proceedings of the 20th IEEE European Test Symposium, 2015

2014

A noise-tolerant master-slave flip-flop.

Yukiya Miura, Yoshihiro Ohkawa

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test.

Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

An On-Chip Digital Environment Monitor for Field Test.

Seiji Kajihara, Yousuke Miyake, Yasuo Sato, Yukiya Miura

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2012

DART: Dependable VLSI test architecture and its implementation.

Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura

Proceedings of the 2012 IEEE International Test Conference, 2012

On-chip temperature and voltage measurement for field testing.

Yukiya Miura, Yasuo Sato, Yousuke Miyake, Seiji Kajihara

Proceedings of the 17th IEEE European Test Symposium, 2012

Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay Detection.

Yoshihiro Ohkawa, Yukiya Miura

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

A supply current testable register string DAC of decoder type.

Masaki Hashizume, Yutaka Hata, Hiroyuki Yotsuyanagi, Yukiya Miura

Proceedings of the 11th International Symposium on Communications and Information Technologies, 2011

Dual Edge Triggered Flip-Flops for Noise Aware Design.

Yukiya Miura

Proceedings of the 16th European Test Symposium, 2011

2010

On estimation of NBTI-Induced delay degradation.

Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura

Proceedings of the 15th European Test Symposium, 2010

2008

Ramp Voltage Testing for Detecting Interconnect Open Faults.

Yukiya Miura

IEICE Trans. Inf. Syst., 2008

Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and <i>X</i> - <i>Y</i> Zoning Method.

Yukiya Miura, Jiro Kato

J. Electron. Test., 2008

Diagnosis of Analog Circuits by Using Multiple Transistors and Data Sampling.

Yukiya Miura, Jiro Kato

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007

Dependable clock distribution for crosstalk aware design.

Yukiya Miura

Proceedings of the 2007 IEEE International Test Conference, 2007

Current Testable Design of Resistor String DACs.

Masaki Hashizume, Yutaka Hata, Tomomi Nishida, Hiroyuki Yotsuyanagi, Yukiya Miura

Proceedings of the 16th Asian Test Symposium, 2007

2006

Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and <i>X</i>-<i>Y</i> Zoning Method: Case Study.

Yukiya Miura

J. Electron. Test., 2006

Fault Diagnosis of Analog Circuits Based on Adaptive Test and Output Characteristics.

Yukiya Miura, Jiro Kato

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Current Testable Design of Resistor String DACs.

Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

A BIC Sensor Capable of Adjusting IDDQ Limit in Tests.

Masato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yukiya Miura

Proceedings of the 15th Asian Test Symposium, 2006

Detection of Interconnect Open Faults with Unknown Values by Ramp Voltage Application.

Yukiya Miura

Proceedings of the 15th Asian Test Symposium, 2006

2005

Characteristics of Fault Diagnosis for Analog Circuits Based on Preset Test.

Yukiya Miura

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004

Analysis and Testing of Bridging Faults in CMOS Synchronous Sequential Circuits.

Yukiya Miura

IEICE Trans. Inf. Syst., 2004

Fault Diagnosis of Analog Circuits by Operation-Region Model and X-Y Zoning Method.

Yukiya Miura

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003

Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and Implementation.

Yukiya Miura, Daisuke Kato

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

A BIST Circuit for IDDQ Tests.

Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits.

Yukiya Miura, Shuichi Seno

J. Electron. Test., 2002

2001

Proposal of an Operation-Region Model for Analyzing Analog and Mixed-Signal Circuits.

Yukiya Miura

Proceedings of the 2nd Latin American Test Workshop, 2001

Internal feedback bridging faults in combinational CMOS circuits: analysis and testing.

Yukiya Miura, Shuichi Seno

Proceedings of the 6th European Test Workshop, 2001

IDDQ Sensing Technique for High Speed IDDQ Testing.

Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits.

Arabi Keshk, Yukiya Miura, Kozo Kinoshita

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

A Low-Loss Built-In Current Sensor.

Yukiya Miura, Hiroshi Yamazaki

J. Electron. Test., 1999

IDDQ Current Dependency on Test Vectors and Bridging Resistance.

Arabi Keshk, Kozo Kinoshita, Yukiya Miura

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits.

Arabi Keshk, Kozo Kinoshita, Yukiya Miura

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

A High-Speed IDDQ Sensor for Low-Voltage ICs.

Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

An IDDQ Sensor Circuit for Low-Voltage ICs.

Yukiya Miura

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996

Real-Time Current Testing for A/D Converters.

Yukiya Miura

IEEE Des. Test Comput., 1996

1995

A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs.

Yukiya Miura, Sachio Naito

IEICE Trans. Inf. Syst., 1995

A Comparative Analysis of Input Stimuli for Testing Mixed-Signal LSIs Based on Curent Testing.

Yukiya Miura

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994

A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit.

Yukiya Miura, Sachio Naito, Kozo Kinoshita

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Design of testing circuit and test generation for built-in current testing.

Yukiya Miura, Yasushi Wada, Kozo Kinoshita

Syst. Comput. Jpn., 1993

1992

Circuit Design for Built-in Current Testing.

Yukiya Miura, Kozo Kinoshita

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1988

Built - in concurrent testing for semiconductor random access memories by concurrently testing cells on a word-line.

Yukiya Miura, Hideo Tamamoto, Yuichi Narita

Syst. Comput. Jpn., 1988

1987

A built-in test for functional testing in semiconductor random access memory.

Yukiya Miura, Hideo Tamamoto, Yuichi Narita

Syst. Comput. Jpn., 1987