Yukihito Oowaki

According to our database, Yukihito Oowaki authored at least 21 papers between 1989 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Caching mechanisms towards single-level storage systems for Internet of Things.

Yosuke Bando, Konosuke Watanabe, Ken-ichi Maeda, Hiroki Kudo, Masahiro Ishiyama, Atsushi Kunimatsu, Hiroto Nakai, Masafumi Takahashi, Yukihito Oowaki

Proceedings of the Symposium on VLSI Circuits, 2015

2014

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing.

Daisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa

IEEE J. Solid State Circuits, 2014

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension.

Konosuke Watanabe, Kenichiro Yoshii, Nobuhiro Kondo, Ken-ichi Maeda, Toshio Fujisawa, Junji Wadatsumi, Daisuke Miyashita, Shouhei Kousai, Yasuo Unekawa, Shinsuke Fujii, Takuma Aoyama, Takayuki Tamura, Atsushi Kunimatsu, Yukihito Oowaki

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput.

Kenta Yasufuku, Naoto Oshiyama, Toshitada Saito, Yukimasa Miyamoto, Yutaka Nakamura, Ryota Terauchi, Atsushi Kondo, Takuma Aoyama, Masafumi Takahashi, Yukihito Oowaki, Ryoichi Bandai

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing.

Daisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011

A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM.

Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki

IEEE J. Solid State Circuits, 2011

Development of low power and high performance application processor (T6G) for multimedia mobile applications.

Yoshiyuki Kitasho, Yu Kikuchi, Takayoshi Shimazawa, Yasuo Ohara, Masafumi Takahashi, Yoshio Masubuchi, Yukihito Oowaki

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm.

Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2007

An automated runtime power-gating scheme.

Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki

Proceedings of the 25th International Conference on Computer Design, 2007

2006

Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems.

Chen Kong Teh, Mototsugu Hamada, Tetsuya Fujita, Hiroyuki Hara, N. Ikumi, Yukihito Oowaki

IEEE Trans. Very Large Scale Integr. Syst., 2006

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling.

Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama

IEEE J. Solid State Circuits, 2006

Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI.

Yukihito Oowaki, Shinichiro Shiratake, Toshihide Fujiyoshi, Mototsugu Hamada, Fumitoshi Hatori, Masami Murakata, Masafumi Takahashi

IEICE Trans. Electron., 2006

2005

A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI.

Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Makoto Takahashi, Yukihito Oowaki

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2001

A 76-mm² 8-Mb chain ferroelectric memory.

Daisaburo Takashima, Yoshiaki Takeuchi, Tadashi Miyakawa, Yasuo Itoh, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Sumiko Mano Doumae, Tohru Ozaki, Hiroyuki Kanaya, Koji Yamakawa, Iwao Kunishima, Yukihito Oowaki

IEEE J. Solid State Circuits, 2001

1999

A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive.

Daisaburo Takashima, Susumu Shuto, Iwao Kunishima, Hiroyuki Takenaka, Yukihito Oowaki, Shin'ichi Tanaka

IEEE J. Solid State Circuits, 1999

1998

Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's.

Daisaburo Takashima, Yukihito Oowaki, Shigeyoshi Watanabe, Kazunori Ohuchi

IEEE J. Solid State Circuits, 1998

1997

A novel power-off mode for a battery-backup DRAM.

Daisaburo Takashima, Yukihito Oowaki

IEEE J. Solid State Circuits, 1997

1994

Standby/active mode logic for sub-1-V operating ULSI memory.

Daisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango

IEEE J. Solid State Circuits, April, 1994

Open/folded bit-line arrangement for ultra-high-density DRAM's.

Daisaburo Takashima, Shigeyoshi Watanabe, Hiroaki Nakano, Yukihito Oowaki, Kazunori Ohuchi

IEEE J. Solid State Circuits, April, 1994

1989

New nibbled-page architecture for high-density DRAMs.

Kenji Numata, Yukihito Oowaki, Yasuo Itoh, Takahiko Hara, Kenji Tsuchida, Masako Ohta, Shigyoshi Watanabe, Kazunori Ohuchi

IEEE J. Solid State Circuits, August, 1989

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode.

Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka

IEEE J. Solid State Circuits, June, 1989