Yukihide Kohira
Orcid: 0000-0002-4063-2497
According to our database1,
Yukihide Kohira
authored at least 35 papers
between 2005 and 2024.
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Bibliography
2024
Development of a Lithography Simulation Tool Set in Various Optical Conditions for Source Mask Optimization.
IEEE Access, 2024
2023
Visualizing Maps of Visitors' Interest for Museum Exhibits with Single-Board Computers.
Proceedings of the 27th International Conference Information Visualisation, 2023
Precise Detection of Changes in Relatively Static Environments for Single-Board Computers.
Proceedings of the 14th IIAI International Congress on Advanced Applied Informatics, 2023
2022
2021
Design of a Knowledge Experience Based Environment for Museum Data Exploration and Knowledge Creation.
Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021
Reliable Night Bear and Boar Detection Based on Training with Pseudo Infrared Images.
Proceedings of 11th International Congress on Advanced Applied Informatics, 2021
Area-efficient Binary and Ternary CNN Accelerator using Random-forest-based Approximation.
Proceedings of the Ninth International Symposium on Computing and Networking, 2021
Proceedings of the 5th IEEE International Conference on Cybernetics, 2021
2020
IEICE Trans. Commun., 2020
Reliable and Efficient Bear-presence Detection based on Region Proposal of Low-resolution.
Proceedings of the 2020 IEEE International Conference on Systems, Man, and Cybernetics, 2020
2019
Clustering Method for Reduction of Area and Power Consumption on Post-Silicon Delay Tuning.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
2016
Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Yield and power improvement method by post-silicon delay tuning and technology mapping.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014
Positive Semidefinite Relaxation and Approximation Algorithm for Triple Patterning Lithography.
Proceedings of the Algorithms and Computation - 25th International Symposium, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
2010
CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
2009
MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
2007
Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005