Yuji Oda
According to our database1,
Yuji Oda
authored at least 4 papers
between 2005 and 2008.
Collaborative distances:
Collaborative distances:
Timeline
2005
2006
2007
2008
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Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2008
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die.
IEEE J. Solid State Circuits, 2008
2007
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits.
IEEE J. Solid State Circuits, 2007
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2005
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005