Yuji Kunitake

According to our database1, Yuji Kunitake authored at least 10 papers between 2007 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
A Selective Replacement Method for Timing-Error-Predicting flip-Flops.
J. Circuits Syst. Comput., 2012

Guidelines for mitigating NBTI degradation in on-chip memories.
Proceedings of the International Symposium on Communications and Information Technologies, 2012

2011
Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI.
IEICE Trans. Electron., 2011

2010
A Replacement Strategy for Canary Flip-Flops.
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

Signal probability control for relieving NBTI in SRAM cells.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009
Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment.
IEICE Trans. Electron., 2009

2008
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008

2007
Exploiting Input Variations for Energy Reduction.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

A Simple Flip-Flop Circuit for Typical-Case Designs for DFM.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Challenges in Evaluations for a Typical-Case Design Methodology.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007


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