Yuichiro Murachi

According to our database, Yuichiro Murachi authored at least 11 papers between 2005 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering.

Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEEE Trans. Very Large Scale Integr. Syst., 2008

A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer.

Yuichiro Murachi, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2008

A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition.

Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Masahiko Yoshimoto

IEICE Trans. Electron., 2008

A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding.

Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding.

Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2006

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture.

Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing.

Junichi Miyakoshi, Yuichiro Murachi, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2006

A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.

Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno

Proceedings of the IFIP VLSI-SoC 2006, 2006

A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering.

Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2005

A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application.

Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Junichi Miyakoshi, Masayuki Miyama, Masahiko Yoshimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation.

Junichi Miyakoshi, Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Masayuki Miyama, Masahiko Yoshimoto

IEICE Trans. Electron., 2005