Yuichiro Miyaoka

According to our database, Yuichiro Miyaoka authored at least 12 papers between 2001 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2006

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs.

Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition.

Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Inf. Syst., 2005

Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis.

Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations.

Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A processor core synthesis system in IP-based SoC design.

Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Instruction set and functional unit synthesis for SIMD processor cores.

Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A cosynthesis algorithm for application specific processors with heterogeneous datapaths.

Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions.

Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions.

Nozomu Togawa, Kyosuke Kasahara, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A hardware/software partitioning algorithm for SIMD processor cores.

Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions.

Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

Area/delay estimation for digital signal processor cores.

Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of ASP-DAC 2001, 2001