Yui Koyanagi

According to our database1, Yui Koyanagi authored at least 6 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
A Light-weight Random Number Generation for Tamper-resistant AES Circuit.
Int. J. Netw. Comput., 2024

A Light-weight and Tamper-resistant AES Implementation by FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
A Cost-Sensitive and Simple Masking Design for Side-Channels.
Proceedings of the IEEE Region 10 Conference, 2023

Effect of High Frequency Noise Using DCMs in FPGA on Power Analysis Attack.
Proceedings of the 22nd International Symposium on Communications and Information Technologies, 2023

A Cost-aware Generation Method of Disposable Random Value Exploiting Parallel S-box Implementation for Tamper-resistant AES Design.
Proceedings of the Eleventh International Symposium on Computing and Networking, CANDAR 2023, 2023

2022
An Extremely Light-Weight Countermeasure to Power Analysis Attack in Dedicated Circuit for AES.
Proceedings of the 19th International SoC Design Conference, 2022


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