Yuh-Kuang Tseng

According to our database, Yuh-Kuang Tseng authored at least 7 papers between 1994 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2007

ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process.

Yuan-Wen Hsiao, Ming-Dou Ker, Po-Yen Chiu, Chun Huang, Yuh-Kuang Tseng

Proceedings of the 2007 IEEE International SOC Conference, 2007

2006

A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process.

Kuo-Hsing Cheng, Kai-Fei Chang, Yu-Lung Lo, Ching-Wen Lai, Yuh-Kuang Tseng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

1999

SRAM.

Yuh-Kuang Tseng

Proceedings of the VLSI Handbook., 1999

A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications.

Yuh-Kuang Tseng, Chung-Yu Wu

IEEE J. Solid State Circuits, 1999

1998

A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications.

Yuh-Kuang Tseng, Chung-Yu Wu

IEEE J. Solid State Circuits, 1998

1996

Bipolar bootstrapped multi-emitter BiCMOS (B²M-BiCMOS) logic for low-voltage applications.

Chung-Yu Wu, Yuh-Kuang Tseng

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1994

Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit.

Yuh-Kuang Tseng, Kuo-Hsing Cheng, Chung-Yu Wu

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994