Yuekang Guo
Affiliations:- Shanghai Jiao Tong University, China
According to our database1,
Yuekang Guo
authored at least 23 papers
between 2019 and 2024.
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Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass Quantizer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization.
IEEE J. Solid State Circuits, September, 2023
A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction.
IEEE J. Solid State Circuits, February, 2023
A Non-Linearity Digital Background Calibration Algorithm with Piece-Wise Linear Functions.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
A Fully Synthesizable Dynamic Voltage Comparator with Time-Domain Offset Calibration.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{\text{VCO}}-\text{Locked}-\text{Loop}$.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Circuits Syst. Signal Process., 2022
A Power-Efficient CMOS Image Sensor with In-Sensor Processing and In-Pixel Gain Calibration.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS.
Circuits Syst. Signal Process., 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
A Latency-Optimized Lookup Table for Nonlinearity Calibration in VCO-Based Sigma-Delta ADCs.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
A Center Frequency Calibration Technique for Ring VCO Exploiting Delay<sup>-1</sup> Detection.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
IEEE Trans. Circuits Syst., 2020
A Low Power Temperature-Compensated Common-Mode Voltage Detector for Dynamic Amplifiers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A Low-Power 10-bit 160-MSample/s DAC in 40-nm CMOS for Baseband Wireless Transmitter.
Proceedings of the 13th IEEE International Conference on ASIC, 2019