Yuejun Zhang
Orcid: 0000-0003-1132-6332
According to our database1,
Yuejun Zhang
authored at least 68 papers
between 2005 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
SI PUF: An SRAM and Inverter-Based PUF With a Bit Error Rate of 0.0053% and 0.073/0.042 pJ/bit.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
Microelectron. J., 2024
Distance optimization KNN and EMD based lightweight hardware IP core design for EEG epilepsy detection.
Microelectron. J., 2024
Integr., 2024
2023
Microelectron. J., September, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
A lightweight convolutional neural network hardware implementation for wearable heart rate anomaly detection.
Comput. Biol. Medicine, March, 2023
Convolutional neural network-based lightweight hardware IP core design for EEG epilepsy prediction.
Microelectron. J., 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
An Architecture of a Single-Event Tolerant D Flip-flop Using Full-Custom Design in 28nm Process.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
A 28 nm 512 Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for high density and low BER cryptographic key in IoT devices.
Microelectron. J., 2022
A configurable detection chip with ±0.6% Inaccuracy for liquid conductivity using dual-frequency sinusoidal signal technique in 65 nm CMOS.
Microelectron. J., 2022
A stable voltage island-driven floorplanning with fixed-outline constraint for low power SoC.
Microelectron. J., 2022
IET Circuits Devices Syst., 2022
A 65nm/0.448 mW EEG processor with parallel architecture SVM and lifting wavelet transform for high-performance and low-power epilepsy detection.
Comput. Biol. Medicine, 2022
2021
A Multimode Configurable Physically Unclonable Function With Bit-Instability-Screening and Power-Gating Strategies.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Integr., 2021
A Three-valued Adder Circuit Implemented in ZnO Memristor with Multi-resistance States.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
A Reliable Multi-information Entropy Glitch PUF Using Schmitt Trigger Sampling Method for IoT Security.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
A HfO2 Ferroelectric Capacitor based 10T2C High Reliability Non-Volatile SRAM for Low Power IoT Applications.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
A Multi-conductance States Memristor-based CNN Circuit Using Quantization Method for Digital Recognition.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A 215-F² Bistable Physically Unclonable Function With an ACF of <0.005 and a Native Bit Instability of 2.05% in 65-nm CMOS Process.
IEEE Trans. Very Large Scale Integr. Syst., 2020
J. Circuits Syst. Comput., 2020
65 nm sub-threshold logic standard cell library using quasi-Schmitt-trigger design scheme and inverse narrow width effect aware sizing.
IET Circuits Devices Syst., 2020
2019
A 0.1-pJ/b and ACF <0.04 Multiple-Valued PUF for Chip Identification Using Bit-Line Sharing Strategy in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Design of anti-key leakage camouflage gate circuit for reverse engineering based on dummy vias.
Microelectron. J., 2019
A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
A 96kb, 0.36V, Energy-Efficient 8T-SRAM with Column-Selection and Shared Buffer-Foot Techniques for EEG Processor.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019
2018
An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process.
Microelectron. J., 2018
Proceedings of the 24th Asia-Pacific Conference on Communications, 2018
2017
A multi-port low-power current mode PUF using MOSFET current-division deviation in 65 nm technology.
Microelectron. J., 2017
A highly reliable lightweight PUF circuit with temperature and voltage compensated for secure chip identification.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
2015
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Operating load based real-time rolling grey forecasting for machine health prognosis in dynamic maintenance schedule.
J. Intell. Manuf., 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing.
IEICE Electron. Express, 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
2013
Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
IEICE Electron. Express, 2012
IEICE Electron. Express, 2012
2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2008
Proceedings of the 8th IEEE International Conference on Advanced Learning Technologies, 2008
2007
Pedagogical Agents for Teacher Intervention in Educational Robotics Classes: Implementation Issues.
Proceedings of the DIGITEL 2007, 2007
2006
Proceedings of the 4th IEEE International Workshop on Wireless and Mobile Technologies in Education, 2006
Proceedings of the Learning by Effective Utilization of Technologies: Facilitating Intercultural Understanding, 2006
Proceedings of the 6th IEEE International Conference on Advanced Learning Technologies, 2006
2005
An Open-ended Framework for Learning Object Metadata Interchange.
Proceedings of the Towards Sustainable and Scalable Educational Innovations Informed by the Learning Sciences, 2005