Yuefeng Cao

Orcid: 0000-0003-1000-9079

According to our database1, Yuefeng Cao authored at least 17 papers between 2016 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
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5
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Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2025
A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer.
IEEE J. Solid State Circuits, February, 2025

2024
A 12-GS/s 12-b 4× Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer.
IEEE J. Solid State Circuits, December, 2024

22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 12b 1GS/s ADC with Lightweight Input Buffer Distortion Background Calibration Achieving >75dB SFDR over PVT.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2021
A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2019
Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
An improved ring amplifier with process- and supply voltage-insensitive dead-zone.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A proved dither-injection method for memory effect in double sampling pipelined ADC.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Bad Data Identification Based on Optimized Local Outlier Detection Algorithm.
Proceedings of the Geo-Spatial Knowledge and Intelligence, 2016


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