Yue Zhang
Orcid: 0000-0001-6893-7199Affiliations:
- Beihang University, Fert Beijing Institute, Beijing, China
- University of Paris-Sud, Orsay, France (PhD 2014)
According to our database1,
Yue Zhang
authored at least 56 papers
between 2011 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A reinforcement learning-based evolutionary algorithm for the unmanned aerial vehicles maritime search and rescue path planning problem considering multiple rescue centers.
Memetic Comput., September, 2024
APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-Level Operations of Quantized Convolutional Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024
Energy-Efficient Satellite Range Scheduling Using a Reinforcement Learning-Based Memetic Algorithm.
IEEE Trans. Aerosp. Electron. Syst., August, 2024
A Novel Search-Based Compute-in-Memory Minimum Values Generation Scheme for Low-Complexity LDPC Min-Sum Decoding.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2024
Generalized Model and Deep Reinforcement Learning-Based Evolutionary Method for Multitype Satellite Observation Scheduling.
IEEE Trans. Syst. Man Cybern. Syst., April, 2024
A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
RSACIM: Resistance Summation Analog Computing in Memory With Accuracy Optimization Scheme Based on MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024
Reinforcement learning-assisted evolutionary algorithm: A survey and research opportunities.
Swarm Evol. Comput., 2024
Data-driven dynamic pricing and inventory management of an omni-channel retailer in an uncertain demand environment.
Expert Syst. Appl., 2024
FRM-CIM: Full-Digital Recursive MAC Computing in Memory System Based on MRAM for Neural Network Applications.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
A Novel 9T1C-SRAM Compute-In-Memory Macro With Count-Less Pulse-Width Modulation Input and ADC-Less Charge-Integration-Count Output.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
Reinforcement Learning-assisted Evolutionary Algorithm: A Survey and Research Opportunities.
CoRR, 2023
TAM: A Computing in Memory based on Tandem Array within STT-MRAM for Energy-Efficient Analog MAC Operation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Reconfigurable Bit-Serial Operation Using Toggle SOT-MRAM for High-Performance Computing in Memory Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2021
Time-Domain Computing in Memory Using Spintronics for Energy-Efficient Convolutional Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Computing-in-memory Scheme with Series Bit-cell in STT-MRAM for Efficient Multi-bit Analog Multiplication.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
2020
A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM.
IEEE Trans. Circuits Syst., 2020
A Diode-Enhanced Scheme for Giant Magnetoresistance Amplification and Reconfigurable Logic.
IEEE Access, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
2018
Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
2017
Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE Trans. Biomed. Circuits Syst., 2016
A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI.
Microelectron. Reliab., 2016
Ultra-low power all spin logic device acceleration based on voltage controlled magnetic anisotropy.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
2015
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Microelectron. Reliab., 2015
Micromachines, 2015
ACM J. Emerg. Technol. Comput. Syst., 2015
Perspectives of racetrack memory based on current-induced domain wall motion: From device to system.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses.
Microelectron. Reliab., 2014
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.
J. Parallel Distributed Comput., 2014
Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A low-cost built-in error correction circuit design for STT-MRAM reliability improvement.
Microelectron. Reliab., 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011