Yuchun Ma

Orcid: 0000-0003-3160-6681

According to our database¹, Yuchun Ma authored at least 91 papers between 2001 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

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In proceedings

Article

PhD thesis

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Links

On csauthors.net:

Bibliography

2023

Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., June, 2023

2022

SNEGAN: Signed Network Embedding by Using Generative Adversarial Nets.

[BibT_eX]

[DOI]

Carlos A. Coello Coello

Maoguo Gong

IEEE Trans. Emerg. Top. Comput. Intell., 2022

2019

AddressNet: Shift-Based Primitives for Efficient Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2019

2018

Shift-based Primitives for Efficient Convolutional Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2018

Lattice-Based Scheduling for Multi-FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2018

2017

基于MPSoC并行调度的矩阵乘法加速算法研究 (Research on Acceleration of Matrix Multiplication Based on Parallel Scheduling on MPSoC).

[BibT_eX]

[DOI]

计算机科学, 2017

Intelligent Composition of Test Papers based on MOOC Learning Data.

[BibT_eX]

[DOI]

Lin Ma

Yuchun Ma

Proceedings of the 10th International Conference on Educational Data Mining, 2017

2016

Modular Placement for Interposer based Multi-FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

F-CNN: An FPGA-based framework for training Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

Relation-oriented resource allocation for multi-accelerator systems.

[BibT_eX]

[DOI]

Teng Yu

Bo Feng

Mark Stillwell

José Gabriel F. Coutinho

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015

HS3-DPG: Hierarchical Simulation for 3-D P/G Network.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

HW/SW Partitioning Algorithm Targeting MPSOC with Dynamic Partial Reconfigurable Fabric.

[BibT_eX]

[DOI]

Chao Zhang

Yuchun Ma

Wayne Luk

Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

2014

On-Chip Hybrid Power Supply System for Wireless Sensor Nodes.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2014

Efficient region-aware P/G TSV planning for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

A universal FPGA-based floating-point matrix processor for mobile systems.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

2013

Thermal-Aware Post Layout Voltage-Island Generation for 3D ICs.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2013

Unification of PR Region floorplanning and Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2013

Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs.

[BibT_eX]

[DOI]

Integr., 2013

Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2013

RALP: Reconvergence-aware layer partitioning for 3D FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Whitespace-aware TSV arrangement in 3D clock tree synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

TSV-aware topology generation for 3D Clock Tree Synthesis.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

Automatic enhanced CDFG generation based on runtime instrumentation.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 17th International Conference on Computer Supported Cooperative Work in Design (CSCWD), 2013

Efficient custom instruction generation based on characterizing of basic blocks.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 17th International Conference on Computer Supported Cooperative Work in Design (CSCWD), 2013

HS3DPG: Hierarchical simulation for 3D P/G network.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Data dependency aware prefetch scheduling for Dynamic Partial reconfigurable designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Incremental 3D NoC synthesis based on physical-aware router merging algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

SMPP: Generic SAT Solver over Reconfigurable Hardware Accelerator.

[BibT_eX]

[DOI]

Zhongda Yuan

Yuchun Ma

Jinian Bian

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

ISBA: An independent set-based algorithm for automated partial reconfiguration module generation.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Thermal-aware power network design for IR drop reduction in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Circuit-level delay modeling considering both TDDB and NBTI.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Novel and efficient min cut based voltage assignment in gate level.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Tree-Based Partitioning Approach for Network-on-Chip Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Computer-Aided Design and Computer Graphics, 2011

Network flow-based simultaneous retiming and slack budgeting for low power design.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

On-chip hybrid power supply system for wireless sensor nodes.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Incremental layout optimization for NoC designs based on MILP formulation.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

Thermal Impacts of Leakage Power in 2D/3D floorplanning.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2010

Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs.

[BibT_eX]

[DOI]

Xu He

Sheqin Dong

Yuchun Ma

Integr., 2010

Simultaneous slack budgeting and retiming for synchronous circuits optimization.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Modern Floorplanning with Boundary Clustering Constraint.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Incremental power optimization for multiple supply voltage design.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Simultaneous buffer and interlayer via planning for 3D floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Multi-objective Floorplanning Based on Fuzzy Logic.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on Fuzzy Systems and Knowledge Discovery, 2009

A novel thermal optimization flow using incremental floorplanning for 3D ICs.

[BibT_eX]

[DOI]

Xin Li

Yuchun Ma

Xianlong Hong

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Investigating the effects of fine-grain three-dimensional integration on microarchitecture design.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2008

IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

MRAPF: Minimum RTT Asymmetric-Path First for Mobile Multi-homed End-to-End Transfer.

[BibT_eX]

[DOI]

Jiemin Liu

Yuchun Ma

Yuan Gao

Proceedings of the Fifth International Conference on Fuzzy Systems and Knowledge Discovery, 2008

LP based white space redistribution for thermal via planning and performance optimization in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

An accurate and efficient probabilistic congestion estimation model in x architecture.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Interconnect Power Optimization Based on Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

A Fast 3D-BSG Algorithm for 3D Packing Problem.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Fine grain 3D integration for microarchitecture design through cube packing exploration.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

An effective buffer planning algorithm for IP based fixed-outline SOC placement.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

VLSI Block Placement With Alignment Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

General Floorplans with L/T-Shaped Blocks Using Corner Block List.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2006

An automated design flow for 3D microarchitecture evaluation.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Buffer planning as an Integral part of floorplanning with consideration of routing congestion.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Buffer Planning Algorithm Based on Partial Clustered Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Performance constrained floorplanning based on partial clustering [IC layout].

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

VLSI block placement with alignment constraints based on corner block list.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Stairway compaction using corner block list and its applications with rectilinear blocks.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2004

Fast Evaluation of Bounded Slice-Line Grid.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2004

Corner block list representation and its application with boundary constraints.

[BibT_eX]

[DOI]

Sci. China Ser. F Inf. Sci., 2004

A buffer planning algorithm for chip-level floorplanning.

[BibT_eX]

[DOI]

Sci. China Ser. F Inf. Sci., 2004

Buffer allocation algorithm with consideration of routing congestion.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A buffer planning algorithm with congestion optimization.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

An integrated floorplanning with an efficient buffer planning algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Physical Design, 2003

Arbitrary convex and concave rectilinear block packing based on corner block list.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Evaluating a bounded slice-line grid assignment in O(nlogn) time.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Dynamic global buffer planning optimization based on detail block locating and congestion analysis.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

A buffer planning algorithm based on dead space redistribution.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2001

Floorplanning with abutment constraints based on corner block list.

[BibT_eX]

[DOI]

Integr., 2001

Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

VLSI floorplanning with boundary constraints based on corner block list.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

Yuchun Ma

Timeline

Legend:

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On csauthors.net:

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