Yuanqing Cheng

Orcid: 0000-0003-2477-314X

According to our database¹, Yuanqing Cheng authored at least 50 papers between 2011 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

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PhD thesis

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Bibliography

2024

Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024

PDG: A Prefetcher for Dynamic Graph Updating.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

MAUnet: Multiscale Attention U-Net for Effective IR Drop Prediction.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

BoCNT: A Bayesian Optimization Framework for Global CNT Interconnect Optimization.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective.

[BibT_eX]

[DOI]

Yuanqing Cheng

Xiaochen Guo

Vasilis F. Pavlidis

Integr., 2022

Thermal Modeling and Design Exploration for Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs.

[BibT_eX]

[DOI]

Kangwei Xu

Yuanqing Cheng

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories.

[BibT_eX]

[DOI]

Proc. IEEE, 2021

Taming Process Variations in CNFET for Efficient Last Level Cache Design.

[BibT_eX]

[DOI]

CoRR, 2021

2020

Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2020

DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength.

[BibT_eX]

[DOI]

Wei Wang

Vasilis F. Pavlidis

Yuanqing Cheng

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

SIP: Boosting Up Graph Computing by Separating the Irregular Property Data.

[BibT_eX]

[DOI]

Jiacheng Ni

Xiaochen Guo

Yuanqing Cheng

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019

An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

2018

An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2018

Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

NEAR: A Novel Energy Aware Replacement Policy for STT-MRAM LLCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Building energy-efficient multi-level cell STT-RAM caches with data compression.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Study of 3-D Power Delivery Networks With Multiple Clock Domains.

[BibT_eX]

[DOI]

Aida Todri-Sanial

Yuanqing Cheng

IEEE Trans. Very Large Scale Integr. Syst., 2016

Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2016

Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Quantitative evaluation of reliability and performance for STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An efficient all-digital IR-Drop Alarmer for DVFS-based SoC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

AES design improvement towards information safety.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Architecture design with STT-RAM: Opportunities and challenges.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

An architecture-level cache simulation framework supporting advanced PMA STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM.

[BibT_eX]

[DOI]

Jacques-Olivier Klein

Weisheng Zhao

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A body-biasing of readout circuit for STT-RAM with improved thermal reliability.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A case of precision-tunable STT-RAM memory design for approximate neural network.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

HARS: A High-Performance Reliable Routing Scheme for 3D NoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2013

A novel method to mitigate TSV electromigration for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

2011

Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Yuanqing Cheng

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