Yuang-Ming Hsu

According to our database, Yuang-Ming Hsu authored at least 7 papers between 1993 and 1995.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

1995

Fault-Tolerant Neural Architectures: The Use of Rotated Operands.

Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Time-Redundant Multiple Computation for Fault-Tolerant Digital Neural Networks.

Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Efficient time redundancy for error correcting inner-product units and convolvers.

Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.

Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

Recomputing by Operand Exchanging: A Time-redundancy Approach for Fault-tolerant Neural Networks.

Yuang-Ming Hsu, Earl E. Swartzlander Jr., Vincenzo Piuri

Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994

Sorting Networks with Built-In Error Correction.

Yuang-Ming Hsu, Earl E. Swartzlander Jr.

Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994

Reliability Estimation for Time Redundant Error Correcting Adders and Multipliers.

Yuang-Ming Hsu, Earl E. Swartzlander Jr.

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993

VLSI Concurrent Error Correcting Adders and Multipliers.

Yuang-Ming Hsu, Earl E. Swartzlander Jr.

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993