Yuan Zhou

According to our database, Yuan Zhou authored at least 13 papers between 2013 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

A Compact Calibration Model for Linearizing CMOS Sample-and-Hold Circuits.

Yanqing Li, Yuan Zhou, Yun Chiu

IEEE Trans. Circuits Syst., 2020

2019

A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC.

Yuan Zhou, Benwei Xu, Yun Chiu

IEEE J. Solid State Circuits, 2019

A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS.

Hongda Xu, Hai Huang, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu

IEEE J. Solid State Circuits, 2019

2018

A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS.

Bo Wu, Shuang Zhu, Yuan Zhou, Yun Chiu

IEEE J. Solid State Circuits, 2018

2017

A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS.

Benwei Xu, Yuan Zhou, Yun Chiu

IEEE J. Solid State Circuits, 2017

28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS.

Hongda Xu, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOS.

Benwei Xu, Yuan Zhou, Yun Chiu

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015

PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC.

Sudipta Sarkar, Yuan Zhou, Brian Elies, Yun Chiu

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector.

Yuan Zhou, Benwei Xu, Yun Chiu

IEEE J. Solid State Circuits, 2015

2014

A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration.

Yuan Zhou, Benwei Xu, Yun Chiu

Proceedings of the Symposium on VLSI Circuits, 2014

PN-assisted deterministic digital calibration of split two-step ADC to over 14-bit accuracy.

Sudipta Sarkar, Yuan Zhou, Yun Chiu

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A 9-bit 215-MS/s folding-flash time-to-digital converter based on redundant remainder number system.

Bo Wu, Shuang Zhu, Yuan Zhou, Yun Chiu

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

Digital calibration of inter-stage nonlinear errors in pipelined SAR ADC.

Yuan Zhou, Yun Chiu

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013