Yuan Xie
Orcid: 0000-0003-2093-1788Affiliations:
- Alibaba DAMO Academy
- University of California at Santa Barbara, CA, USA (former)
- Pennsylvania State University, Philadelphia, PA, USA (2003 - 2013)
- Princeton University, Princeton, NJ, USA (PhD 2002)
According to our database1,
Yuan Xie
authored at least 559 papers
between 2000 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on orcid.org
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on ece.ucsb.edu
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on dl.acm.org
On csauthors.net:
Bibliography
2024
Optimizing NVMe Storage for Large-Scale Deployment: Key Technologies and Strategies in Alibaba Cloud.
IEEE Micro, 2024
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
2023
Proc. IEEE, December, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
IEEE Trans. Parallel Distributed Syst., September, 2023
IEEE Trans. Neural Networks Learn. Syst., June, 2023
Exploring Adversarial Attack in Spiking Neural Networks With Spike-Compatible Gradient.
IEEE Trans. Neural Networks Learn. Syst., May, 2023
IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023
SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
E-Booster: A Field-Programmable Gate Array-Based Accelerator for Secure Tree Boosting Using Additively Homomorphic Encryption.
IEEE Micro, 2023
ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration.
IEEE J. Solid State Circuits, 2023
TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes.
IEEE J. Solid State Circuits, 2023
ACM Comput. Surv., 2023
CoRR, 2023
High-performance and Scalable Software-based NVMe Virtualization Mechanism with I/O Queues Passthrough.
CoRR, 2023
Proceedings of the 28th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming, 2023
Proceedings of the Sixth Conference on Machine Learning and Systems, 2023
DF-GAS: a Distributed FPGA-as-a-Service Architecture towards Billion-Scale Graph-based Approximate Nearest Neighbor Search.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
TT-GNN: Efficient On-Chip Graph Neural Network Training via Embedding Reformation and Hardware Optimization.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
RM-STC: Row-Merge Dataflow Inspired GPU Sparse Tensor Core for Energy-Efficient Sparse Acceleration.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
ECSSD: Hardware/Data Layout Co-Designed In-Storage-Computing Architecture for Extreme Classification.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
HBP: Hierarchically Balanced Pruning and Accelerator Co-Design for Efficient DNN Inference.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
CHAM: A Customized Homomorphic Encryption Accelerator for Fast Matrix-Vector Product.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2022
STPAcc: Structural TI-Based Pruning for Accelerating Distance-Related Algorithms on CPU-FPGA Platforms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Efficient Processing of Sparse Tensor Decomposition via Unified Abstraction and PE-Interactive Architecture.
IEEE Trans. Computers, 2022
IEEE Trans. Computers, 2022
IEEE Trans. Computers, 2022
Proc. VLDB Endow., 2022
A Comprehensive and Modularized Statistical Framework for Gradient Norm Equality in Deep Neural Networks.
IEEE Trans. Pattern Anal. Mach. Intell., 2022
SaARSP: An Architecture for Systolic-Array Acceleration of Recurrent Spiking Neural Networks.
ACM J. Emerg. Technol. Comput. Syst., 2022
Neurocomputing, 2022
CoRR, 2022
Cost-Aware Exploration for Chiplet-Based Architecture with Advanced Packaging Technologies.
CoRR, 2022
The Spike Gating Flow: A Hierarchical Structure Based Spiking Neural Network for Online Gesture Recognition.
CoRR, 2022
CoRR, 2022
IEEE Comput. Archit. Lett., 2022
Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network.
IEEE Access, 2022
IEEE Access, 2022
OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs.
IEEE Access, 2022
Proceedings of the 2022 USENIX Annual Technical Conference, 2022
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022
Understanding GNN Computational Graph: A Coordinated Computation, IO, and Memory Perspective.
Proceedings of the Fifth Conference on Machine Learning and Systems, 2022
AutoComm: A Framework for Enabling Efficient Communication in Distributed Quantum Programs.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
BEACON: Scalable Near-Data-Processing Accelerators for Genome Analysis near Memory Pool with the CXL Support.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
184QPS/W 64Mb/mm<sup>2</sup>3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A synthesis framework for stitching surface code with superconducting quantum devices.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
INSPIRE: in-storage private information retrieval via protocol and architecture co-design.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
Proceedings of the Thirty-First International Joint Conference on Artificial Intelligence, 2022
Proceedings of the 34th IEEE International Conference on Tools with Artificial Intelligence, 2022
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio.
Proceedings of the 28th IEEE International Conference on Parallel and Distributed Systems, 2022
Proceedings of the Tenth International Conference on Learning Representations, 2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Accelerating Spatiotemporal Supervised Training of Large-Scale Spiking Neural Networks on GPU.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
High-level synthesis performance prediction using GNNs: benchmarking, modeling, and advancing.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Alleviating datapath conflicts and design centralization in graph analytics acceleration.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Shfl-BW: accelerating deep neural network inference with tensor-core aware weight pruning.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022
A one-for-all and <i>o</i>(<i>v</i> log(<i>v</i> ))-cost solution for parallel merge style operations on sorted key-value arrays.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022
Paulihedral: a generalized block-wise compiler optimization framework for Quantum simulation kernels.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022
2021
Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning.
ACM Trans. Design Autom. Electr. Syst., 2021
Effective and Efficient Batch Normalization Using a Few Uncorrelated Data for Statistics Estimation.
IEEE Trans. Neural Networks Learn. Syst., 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE J. Sel. Top. Signal Process., 2021
Erratum to "Evolver: a Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning".
IEEE J. Solid State Circuits, 2021
Evolver: A Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning.
IEEE J. Solid State Circuits, 2021
Neurocomputing, 2021
Neurocomputing, 2021
Recap of the 39th Edition of the International Conference on Computer-Aided Design (ICCAD 2020).
IEEE Des. Test, 2021
Mitigating Noise-Induced Gradient Vanishing in Variational Quantum Algorithm Training.
CoRR, 2021
Program-to-Circuit: Exploiting GNNs for Program Representation and Circuit Translation.
CoRR, 2021
Efficient Sparse Matrix Kernels based on Adaptive Workload-Balancing and Parallel-Reduction.
CoRR, 2021
CoRR, 2021
Π-RT: A Runtime Framework to Enable Energy-Efficient Real-Time Robotic Vision Applications on Heterogeneous Architectures.
Computer, 2021
IEEE Comput. Archit. Lett., 2021
Proceedings of the 2021 USENIX Annual Technical Conference, 2021
Efficient tensor core-based GPU kernels for structured sparsity under reduced precision.
Proceedings of the International Conference for High Performance Computing, 2021
Proceedings of the PPoPP '21: 26th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2021
Proceedings of the 15th USENIX Symposium on Operating Systems Design and Implementation, 2021
Proceedings of the NANOCOM '21: The Eighth Annual ACM International Conference on Nanoscale Computing and Communication, Virtual Event, Italy, September 7, 2021
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
NeuroMeter: An Integrated Power, Area, and Timing Modeling Framework for Machine Learning Accelerators Industry Track Paper.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
IRONMAN: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the 21st IEEE/ACM International Symposium on Cluster, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs.
IEEE Trans. Computers, 2020
ACM Trans. Archit. Code Optim., 2020
Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey.
Proc. IEEE, 2020
Proc. ACM Program. Lang., 2020
Training high-performance and large-scale deep neural networks with full 8-bit integers.
Neural Networks, 2020
Comparing SNNs and RNNs on neuromorphic vision datasets: Similarities and differences.
Neural Networks, 2020
Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation.
IEEE J. Solid State Circuits, 2020
A Case for 3D Integrated System Design for Neuromorphic Computing and AI Applications.
Int. J. Semantic Comput., 2020
CoRR, 2020
IEEE Comput. Archit. Lett., 2020
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
SAGA-Bench: Software and Hardware Characterization of Streaming Graph Analytics Workloads.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
Timely: Pushing Data Movements And Interfaces In Pim Accelerators Towards Local And In Time Domain.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
Proceedings of the 37th International Conference on Machine Learning, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
Fulcrum: A Simplified Control and Access Mechanism Toward Flexible and Practical In-Situ Accelerators.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
Proceedings of the IEEE Hot Chips 32 Symposium, 2020
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
INVITED: Computation on Sparse Neural Networks and its Implications for Future Hardware.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020
2019
PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2019
DASM: Data-Streaming-Based Computing in Nonvolatile Memory Architecture for Embedded System.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory.
IEEE Trans. Parallel Distributed Syst., 2019
IEEE Trans. Neural Networks Learn. Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
CoRR, 2019
AccD: A Compiler-based Framework for Accelerating Distance-related Algorithms on CPU-FPGA Platforms.
CoRR, 2019
SANQ: A Simulation Framework for Architecting Noisy Intermediate-Scale Quantum Computing System.
CoRR, 2019
Neural Network Model Extraction Attacks in Edge Devices by Hearing Architectural Hints.
CoRR, 2019
NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs.
IEEE Comput. Archit. Lett., 2019
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems.
Proceedings of the 21st ACM/IEEE International Workshop on System Level Interconnect Prediction, 2019
SuperMem: Enabling Application-transparent Secure Persistent Memory with Low Overheads.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Sparse Tensor Core: Algorithm and Hardware Co-Design for Vector-wise Sparse Neural Networks on Modern GPUs.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
MEDAL: Scalable DIMM based Near Data Processing Accelerator for DNA Seeding Algorithm.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Proceedings of the 7th International Conference on Learning Representations, 2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019
CNNWire: Boosting Convolutional Neural Network with Winograd on ReRAM based Accelerators.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019
FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019
Learning the sparsity for ReRAM: mapping and pruning sparse neural network for ReRAM based accelerator.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Proceedings of the Thirty-Third AAAI Conference on Artificial Intelligence, 2019
2018
Performance Evaluation and Optimization of HBM-Enabled GPU for Data-Intensive Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Securing Emerging Nonvolatile Main Memory With Fast and Energy-Efficient AES In-Memory Implementation.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors.
IEEE Micro, 2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Structurally Sparsified Backward Propagation for Faster Long Short-Term Memory Training.
CoRR, 2018
CoRR, 2018
PIRT: A Runtime Framework to Enable Energy-Efficient Real-Time Robotic Applications on Heterogeneous Architectures.
CoRR, 2018
Bridging the Gap Between Neural Networks and Neuromorphic Hardware with A Neural Network Compiler.
CoRR, 2018
IEEE Comput. Archit. Lett., 2018
Proceedings of the Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems 2018, 2018
Proceedings of the Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems 2018, 2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Persistence Parallelism Optimization: A Holistic Approach from Memory Bus to RDMA Network.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Proceedings of the International Symposium on Memory Systems, 2018
AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
SNrram: an efficient sparse neural network computation architecture based on resistive random-access memory.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
Bridge the Gap between Neural Networks and Neuromorphic Hardware with a Neural Network Compiler.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
Cost-efficient 3D Integration to Hinder Reverse Engineering During and After Manufacturing.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems.
ACM Trans. Embed. Comput. Syst., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Micro, 2017
IEEE Des. Test, 2017
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
Cost-effective design of scalable high-performance systems using active and passive interposers.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
PRESCOTT: Preset-based cross-point architecture for spin-orbit-torque magnetic random access memory.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
ACM Trans. Design Autom. Electr. Syst., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power.
IEEE Micro, 2016
J. Comput. Sci. Technol., 2016
CNNLab: a Novel Parallel Framework for Neural Networks using GPU and FPGA-a Practical Study with Trade-off Analysis.
CoRR, 2016
Redesigning software and systems for non-volatile processors on self-powered devices.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor.
Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 2016 International Conference on Compilers, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01747-6, 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
ACM Trans. Design Autom. Electr. Syst., 2015
Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference.
ACM Trans. Design Autom. Electr. Syst., 2015
Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems.
ACM Trans. Design Autom. Electr. Syst., 2015
Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach.
IEEE Trans. Multi Scale Comput. Syst., 2015
ACM Trans. Archit. Code Optim., 2015
EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors.
ACM Trans. Archit. Code Optim., 2015
IEEE Micro, 2015
ACM J. Emerg. Technol. Comput. Syst., 2015
IPSJ Trans. Syst. LSI Des. Methodol., 2015
IEEE Comput. Archit. Lett., 2015
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Exploring memory controller configurations for many-core systems with 3D stacked DRAMs.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures.
Proceedings of the 29th ACM on International Conference on Supercomputing, 2015
Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 2015 International Conference on Compilers, 2015
Heterogeneous architecture design with emerging 3D and non-volatile memory technologies.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
ACM Trans. Design Autom. Electr. Syst., 2014
Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
ACM Trans. Archit. Code Optim., 2014
ACM Trans. Archit. Code Optim., 2014
ACM Trans. Archit. Code Optim., 2014
Testable cross-power domain interface (CPDI) circuit design in monolithic 3D technology.
ACM J. Emerg. Technol. Comput. Syst., 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
An Embedded Co-AdaBoost based construction of software document relation coupled resource spaces for cyber-physical society.
Future Gener. Comput. Syst., 2014
IEEE Des. Test, 2014
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
SwimmingLane: A composite approach to mitigate voltage droop effects in 3D power delivery network.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
2013
Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface.
ACM Trans. Archit. Code Optim., 2013
ACM Trans. Archit. Code Optim., 2013
A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies.
ACM Trans. Archit. Code Optim., 2013
Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory.
ACM J. Emerg. Technol. Comput. Syst., 2013
ACM J. Emerg. Technol. Comput. Syst., 2013
Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits.
IET Circuits Devices Syst., 2013
Kiln: closing the performance gap between systems with and without persistence support.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
i<sup>2</sup>WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Designing energy-efficient NoC for real-time embedded systems through slack optimization.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2012
ACM Trans. Design Autom. Electr. Syst., 2012
Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling.
ACM Trans. Embed. Comput. Syst., 2012
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/Vdd Library and Device Sizing.
J. Electr. Comput. Eng., 2012
An Embedded Co-AdaBoost and Its Application in Classification of Software Document Relation.
Proceedings of the Eighth International Conference on Semantics, Knowledge and Grids, 2012
Proceedings of the SC Conference on High Performance Computing Networking, 2012
NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Optimizing bandwidth and power of graphics memory with hybrid memory technologies and adaptive data migration.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Mitigating electromigration of power supply networks using bidirectional current stress.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Point and discard: a hard-error-tolerant architecture for non-volatile last level caches.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model.
IEEE Trans. Dependable Secur. Comput., 2011
Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation.
IEEE Trans. Dependable Secur. Comput., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Hybrid checkpointing using emerging nonvolatile memories for future exascale systems.
ACM Trans. Archit. Code Optim., 2011
IET Comput. Digit. Tech., 2011
Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.
IET Comput. Digit. Tech., 2011
Found. Trends Electron. Des. Autom., 2011
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
IEEE Des. Test Comput., 2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
J. Signal Process. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
ACM Trans. Archit. Code Optim., 2010
Microelectron. J., 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support.
Proceedings of the Conference on High Performance Computing Networking, 2010
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Parametric yield driven resource binding in behavioral synthesis with multi-<i>V</i><sub><i>th</i></sub><i>/V</i><sub><i>dd</i></sub> library.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Minimizing leakage power in aging-bounded high-level synthesis with design time multi-<i>V</i><sub><i>th</i></sub> assignment.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Architectural benefits and design challenges for three-dimensional integrated circuits.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
Proceedings of the IEEE International Conference on 3D System Integration, 2010
Proceedings of the IEEE International Conference on 3D System Integration, 2010
2009
IEEE Trans. Dependable Secur. Comput., 2009
IEEE Trans. Computers, 2009
ACM J. Emerg. Technol. Comput. Syst., 2009
<i>New-Age</i>: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components.
Int. J. Parallel Program., 2009
IEICE Trans. Electron., 2009
IEEE Des. Test Comput., 2009
IEEE Des. Test Comput., 2009
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Exploration of 3D stacked L2 cache design for high performance and efficient thermal control.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009
Proceedings of the 27th International Conference on Computer Design, 2009
3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis.
Proceedings of the 27th International Conference on Computer Design, 2009
Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 2009 International Conference on Compilers, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs).
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the IEEE International Conference on 3D System Integration, 2009
Proceedings of the IEEE International Conference on 3D System Integration, 2009
Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs.
Proceedings of the IEEE International Conference on 3D System Integration, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
ACM J. Emerg. Technol. Comput. Syst., 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Thermal-aware Design Considerations for Application-Specific Instruction Set Processor.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the 26th International Conference on Computer Design, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.
Proceedings of the 45th Design Automation Conference, 2008
Variability-driven module selection with joint design time optimization and post-silicon tuning.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
A novel dimensionally-decomposed router for on-chip communication in 3D architectures.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007
Proceedings of the 25th International Conference on Computer Design, 2007
Proceedings of the 25th International Conference on Computer Design, 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design.
J. VLSI Signal Process., 2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
ACM J. Emerg. Technol. Comput. Syst., 2006
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach.
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 2004 Design, 2004
2003
J. Circuits Syst. Comput., 2003
Proceedings of the VLSI-SOC: From Systems to Chips, 2003
Proceedings of the 2003 Data Compression Conference (DCC 2003), 2003
2002
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
2001
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001
Proceedings of the Data Compression Conference, 2001
Allocation and scheduling of conditional task graph in hardware/software co-synthesis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000