Yuan Xie

Hezi Zhang

Gian Giacomo Guerreschi

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

INSPIRE: in-storage private information retrieval via protocol and architecture co-design.

[BibT_eX]

[DOI]

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network.

[BibT_eX]

[DOI]

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

DIMMining: pruning-efficient and parallel graph mining on near-memory-computing.

[BibT_eX]

[DOI]

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Survey on Graph Neural Network Acceleration: An Algorithmic Perspective.

[BibT_eX]

[DOI]

Proceedings of the Thirty-First International Joint Conference on Artificial Intelligence, 2022

Compact Multi-level Sparse Neural Networks with Input Independent Dynamic Rerouting.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Tools with Artificial Intelligence, 2022

Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Parallel and Distributed Systems, 2022

Effective Model Sparsification by Scheduled Grow-and-Prune Methods.

[BibT_eX]

[DOI]

Proceedings of the Tenth International Conference on Learning Representations, 2022

AI-assisted Synthesis in Next Generation EDA: Promises, Challenges, and Prospects.

[BibT_eX]

[DOI]

Nan Wu

Cong Hao

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2022 ICCAD CAD Contest Problem C: Microarchitecture Design Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Accelerating Spatiotemporal Supervised Training of Large-Scale Spiking Neural Networks on GPU.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

High-level synthesis performance prediction using GNNs: benchmarking, modeling, and advancing.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Alleviating datapath conflicts and design centralization in graph analytics acceleration.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Shfl-BW: accelerating deep neural network inference with tensor-core aware weight pruning.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Heuristic adaptability to input dynamics for SpMM on CPUs.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

CHEX: CHannel EXploration for CNN Model Compression.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

A one-for-all and o(v log(v ))-cost solution for parallel merge style operations on sorted key-value arrays.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

DOTA: detect and omit weak attentions for scalable transformer acceleration.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

Paulihedral: a generalized block-wise compiler optimization framework for Quantum simulation kernels.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

2021

Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2021

Effective and Efficient Batch Normalization Using a Few Uncorrelated Data for Statistics Estimation.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., 2021

A Novel, Efficient Implementation of a Local Binary Convolutional Neural Network.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Rescuing RRAM-Based Computing From Static and Dynamic Faults.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Practical Attacks on Deep Neural Networks by Memory Trojaning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Fast Search of the Optimal Contraction Sequence in Tensor Networks.

[BibT_eX]

[DOI]

IEEE J. Sel. Top. Signal Process., 2021

Erratum to "Evolver: a Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning".

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2021

Evolver: A Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2021

Training and inference for integer-based semantic segmentation network.

[BibT_eX]

[DOI]

Neurocomputing, 2021

Tensor train decomposition for solving large-scale linear equations.

[BibT_eX]

[DOI]

Neurocomputing, 2021

Recap of the 39th Edition of the International Conference on Computer-Aided Design (ICCAD 2020).

[BibT_eX]

[DOI]

IEEE Des. Test, 2021

Load-balanced Gather-scatter Patterns for Sparse Deep Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2021

Towards Efficient Ansatz Architecture for Variational Quantum Algorithms.

[BibT_eX]

[DOI]

CoRR, 2021

Mapping Surface Code to Superconducting Quantum Processors.

[BibT_eX]

[DOI]

Anbang Wu

Hezi Zhang

Gian Giacomo Guerreschi

CoRR, 2021

QECV: Quantum Error Correction Verification.

[BibT_eX]

[DOI]

Anbang Wu

Hezi Zhang

Gian Giacomo Guerreschi

CoRR, 2021

Mitigating Noise-Induced Gradient Vanishing in Variational Quantum Algorithm Training.

[BibT_eX]

[DOI]

CoRR, 2021

Transformer Acceleration with Dynamic Sparse Attention.

[BibT_eX]

[DOI]

CoRR, 2021

Program-to-Circuit: Exploiting GNNs for Program Representation and Circuit Translation.

[BibT_eX]

[DOI]

CoRR, 2021

Efficient Sparse Matrix Kernels based on Adaptive Workload-Balancing and Parallel-Reduction.

[BibT_eX]

[DOI]

CoRR, 2021

MPU: Towards Bandwidth-abundant SIMT Processor via Near-bank Computing.

[BibT_eX]

[DOI]

CoRR, 2021

A Case for 3D Integrated System Design for Neuromorphic Computing & AI Applications.

[BibT_eX]

[DOI]

CoRR, 2021

Π-RT: A Runtime Framework to Enable Energy-Efficient Real-Time Robotic Vision Applications on Heterogeneous Architectures.

[BibT_eX]

[DOI]

Computer, 2021

Hardware Acceleration for GCNs via Bidirectional Fusion.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2021

Palleon: A Runtime System for Efficient Video Processing toward Dynamic Class Skew.

[BibT_eX]

[DOI]

Proceedings of the 2021 USENIX Annual Technical Conference, 2021

Efficient tensor core-based GPU kernels for structured sparsity under reduced precision.

[BibT_eX]

[DOI]

Proceedings of the International Conference for High Performance Computing, 2021

EGEMM-TC: accelerating scientific computing on tensor cores with extended precision.

[BibT_eX]

[DOI]

Proceedings of the PPoPP '21: 26th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2021

GNNAdvisor: An Adaptive and Efficient Runtime System for GNN Acceleration on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 15th USENIX Symposium on Operating Systems Design and Implementation, 2021

On the Co-Design of Quantum Software and Hardware.

[BibT_eX]

[DOI]

Proceedings of the NANOCOM '21: The Eighth Annual ACM International Conference on Nanoscale Computing and Communication, Virtual Event, Italy, September 7, 2021

ENMC: Extreme Near-Memory Classification via Approximate Screening.

[BibT_eX]

[DOI]

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Improving Streaming Graph Processing Performance using Input Knowledge.

[BibT_eX]

[DOI]

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Overcoming the Memory Hierarchy Inefficiencies in Graph Processing Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

SpaceA: Sparse Matrix Vector Multiplication on Processing-in-Memory Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

NeuroMeter: An Integrated Power, Area, and Timing Modeling Framework for Machine Learning Accelerators Industry Track Paper.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

IRONMAN: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning.

[BibT_eX]

[DOI]

Nan Wu

Patricia Gonzalez-Guerrero

Cong Hao

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

SEALing Neural Network Models in Encrypted Deep Learning Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

TiAcc: Triangle-inequality based Hardware Accelerator for K-means on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE/ACM International Symposium on Cluster, 2021

2020

SemiMap: A Semi-Folded Convolution Mapping for Speed-Overhead Balance on Crossbars.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2020

Scanning the Issue.

[BibT_eX]

[DOI]

H.-S. Philip Wong

Kerem Akarvardar

Dimitri A. Antoniadis

Proc. IEEE, 2020

Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey.

[BibT_eX]

[DOI]

Proc. IEEE, 2020

Projection-based runtime assertions for testing and debugging Quantum programs.

[BibT_eX]

[DOI]

Proc. ACM Program. Lang., 2020

Training high-performance and large-scale deep neural networks with full 8-bit integers.

[BibT_eX]

[DOI]

Neural Networks, 2020

Comparing SNNs and RNNs on neuromorphic vision datasets: Similarities and differences.

[BibT_eX]

[DOI]

Neural Networks, 2020

Rethinking the performance comparison between SNNS and ANNS.

[BibT_eX]

[DOI]

Neural Networks, 2020

Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

A Case for 3D Integrated System Design for Neuromorphic Computing and AI Applications.

[BibT_eX]

[DOI]

Int. J. Semantic Comput., 2020

Rubik: A Hierarchical Architecture for Efficient Graph Learning.

[BibT_eX]

[DOI]

CoRR, 2020

SEALing Neural Network Models in Secure Deep Learning Accelerators.

[BibT_eX]

[DOI]

CoRR, 2020

GNNAdvisor: An Efficient Runtime System for GNN Acceleration on GPUs.

[BibT_eX]

[DOI]

CoRR, 2020

Computation on Sparse Neural Networks: an Inspiration for Future Hardware.

[BibT_eX]

[DOI]

CoRR, 2020

Memristor Hardware-Friendly Reinforcement Learning.

[BibT_eX]

[DOI]

CoRR, 2020

Characterizing and Understanding GCNs on GPU.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2020

NMTSim: Transaction-Command Based Simulator for New Memory Technology Devices.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2020

DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

SAGA-Bench: Software and Hardware Characterization of Streaming Graph Analytics Workloads.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

SmartExchange: Trading Higher-cost Memory Storage/Access for Lower-cost Computation.

[BibT_eX]

[DOI]

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Timely: Pushing Data Movements And Interfaces In Pim Accelerators Towards Local And In Time Domain.

[BibT_eX]

[DOI]

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture.

[BibT_eX]

[DOI]

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product.

[BibT_eX]

[DOI]

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Boosting Deep Neural Network Efficiency with Dual-Module Inference.

[BibT_eX]

[DOI]

Proceedings of the 37th International Conference on Machine Learning, 2020

NEST: DIMM based Near-Data-Processing Accelerator for K-mer Counting.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

fuseGNN: Accelerating Graph Convolutional Neural Network Training on GPGPU.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

HyGCN: A GCN Accelerator with Hybrid Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Fulcrum: A Simplified Control and Access Mechanism Toward Flexible and Practical In-Situ Accelerators.

[BibT_eX]

[DOI]

Marzieh Lenjani

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Xuantie-910: Innovating Cloud and Edge Computing by RISC-V.

[BibT_eX]

[DOI]

Proceedings of the IEEE Hot Chips 32 Symposium, 2020

MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Taming Unstructured Sparsity on GPUs via Latency-Aware Optimization.

[BibT_eX]

[DOI]

Maohua Zhu

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

INVITED: Computation on Sparse Neural Networks and its Implications for Future Hardware.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Eliminating Redundant Computation in Noisy Quantum Computing Simulation.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Towards Efficient Superconducting Quantum Processor Architecture Design.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

DeepSniffer: A DNN Model Extraction Framework Based on Learning Architectural Hints.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

DARB: A Density-Adaptive Regular-Block Pruning for Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020

2019

PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

DASM: Data-Streaming-Based Computing in Nonvolatile Memory Architecture for Embedded System.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2019

L1-Norm Batch Normalization for Efficient Training of Deep Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., 2019

GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Emerging Memory Technologies.

[BibT_eX]

[DOI]

IEEE Micro, 2019

Network-on-Chip Design Guidelines for Monolithic 3-D Integration.

[BibT_eX]

[DOI]

Itir Akgun

IEEE Micro, 2019

Poq: Projection-based Runtime Assertions for Debugging on a Quantum Computer.

[BibT_eX]

[DOI]

CoRR, 2019

DARB: A Density-Aware Regular-Block Pruning for Deep Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2019

AccD: A Compiler-based Framework for Accelerating Distance-related Algorithms on CPU-FPGA Platforms.

[BibT_eX]

[DOI]

CoRR, 2019

SANQ: A Simulation Framework for Architecting Noisy Intermediate-Scale Quantum Computing System.

[BibT_eX]

[DOI]

CoRR, 2019

Neural Network Model Extraction Attacks in Edge Devices by Hearing Architectural Hints.

[BibT_eX]

[DOI]

CoRR, 2019

QGAN: Quantized Generative Adversarial Networks.

[BibT_eX]

[DOI]

CoRR, 2019

A Secure and Persistent Memory System for Non-volatile Memory.

[BibT_eX]

[DOI]

Pengfei Zuo

Yu Hua

CoRR, 2019

NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2019

Power Profiling of Modern Die-Stacked Memory.

[BibT_eX]

[DOI]

Amin Farmahini Farahani

Sudhanva Gurumurthi

Michael Ignatowski

IEEE Comput. Archit. Lett., 2019

CRISP: Center for Research on Intelligent Storage and Processing-in-Memory.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems.

[BibT_eX]

[DOI]

Itir Akgun

Proceedings of the 21st ACM/IEEE International Workshop on System Level Interconnect Prediction, 2019

SuperMem: Enabling Application-transparent Secure Persistent Memory with Low Overheads.

[BibT_eX]

[DOI]

Pengfei Zuo

Yu Hua

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Sparse Tensor Core: Algorithm and Hardware Co-Design for Vector-wise Sparse Neural Networks on Modern GPUs.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

MEDAL: Scalable DIMM based Near Data Processing Accelerator for DNA Seeding Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Dynamic Sparse Graph for Efficient Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Learning Representations, 2019

Analysis and Optimization of the Memory Hierarchy for Graph Processing Workloads.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Ouroboros: An Inference Engine for Deep Learning Based TTS on Embedded Devices.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

CNNWire: Boosting Convolutional Neural Network with Winograd on ReRAM based Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Memory Trojan Attack on Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

CORN: In-Buffer Computing for Binary Neural Network.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Memory-Bound Proof-of-Work Acceleration for Blockchain Applications.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Tackling the Qubit Mapping Problem for NISQ-Era Quantum Devices.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

Learning the sparsity for ReRAM: mapping and pruning sparse neural network for ReRAM based accelerator.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Direct Training for Spiking Neural Networks: Faster, Larger, Better.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Third AAAI Conference on Artificial Intelligence, 2019

2018

Performance Evaluation and Optimization of HBM-Enabled GPU for Data-Intensive Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Securing Emerging Nonvolatile Main Memory With Fast and Energy-Efficient AES In-Memory Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes.

[BibT_eX]

[DOI]

Ing-Chao Lin

Yun Kae Law

IEEE Trans. Very Large Scale Integr. Syst., 2018

An Instruction Set Architecture for Machine Learning.

[BibT_eX]

[DOI]

ACM Trans. Comput. Syst., 2018

MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors.

[BibT_eX]

[DOI]

IEEE Micro, 2018

Die Stacking Is Happening.

[BibT_eX]

[DOI]

Xing Hu

IEEE Micro, 2018

Stuck-at Fault Tolerance in RRAM Computing Systems.

[BibT_eX]

[DOI]

Yu Wang

Huazhong Yang

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Batch Normalization Sampling.

[BibT_eX]

[DOI]

CoRR, 2018

In-memory multiplication engine with SOT-MRAM based stochastic computing.

[BibT_eX]

[DOI]

CoRR, 2018

Structurally Sparsified Backward Propagation for Faster Long Short-Term Memory Training.

[BibT_eX]

[DOI]

CoRR, 2018

L1-Norm Batch Normalization for Efficient Training of Deep Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2018

PIRT: A Runtime Framework to Enable Energy-Efficient Real-Time Robotic Applications on Heterogeneous Architectures.

[BibT_eX]

[DOI]

CoRR, 2018

Bridging the Gap Between Neural Networks and Neuromorphic Hardware with A Neural Network Compiler.

[BibT_eX]

[DOI]

CoRR, 2018

Exploring Core and Cache Hierarchy Bottlenecks in Graph Processing Workloads.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

Crossbar-Aware Neural Network Pruning.

[BibT_eX]

[DOI]

IEEE Access, 2018

HitNet: Hybrid Ternary Recurrent Neural Network.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems 2018, 2018

TETRIS: TilE-matching the TRemendous Irregular Sparsity.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems 2018, 2018

SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Persistence Parallelism Optimization: A Holistic Approach from Memory Bus to RDMA Network.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

GraphIA: an in-situ accelerator for large-scale graph processing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2018

AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

SNrram: an efficient sparse neural network computation architecture based on resistive random-access memory.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

RADAR: a 3D-reRAM based DNA alignment accelerator architecture.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

Packet pump: overcoming network bottleneck in on-chip interconnects for GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing.

[BibT_eX]

[DOI]

Kaisheng Ma

Xueqing Li

Mahmut Taylan Kandemir

Jack Sampson

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

Bridge the Gap between Neural Networks and Neuromorphic Hardware with a Neural Network Compiler.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

Cost-efficient 3D Integration to Hinder Reverse Engineering During and After Manufacturing.

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017

Thermomechanical Stress-Aware Management for 3-D IC Designs.

[BibT_eX]

[DOI]

Eren Kursun

IEEE Trans. Very Large Scale Integr. Syst., 2017

Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2017

DLAU: A Scalable Deep Learning Accelerator Unit on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Software-Hardware Codesign for Efficient Neural Network Acceleration.

[BibT_eX]

[DOI]

IEEE Micro, 2017

Overview of 3-D Architecture Design Opportunities and Techniques.

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

Incidental computing on IoT nonvolatile processors.

[BibT_eX]

[DOI]

Mahmut Taylan Kandemir

Srivatsa Rangachar Srinivasa

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

DRISA: a DRAM-based reconfigurable in-situ accelerator.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes.

[BibT_eX]

[DOI]

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Cost-effective design of scalable high-performance systems using active and passive interposers.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

PRESCOTT: Preset-based cross-point architecture for spin-orbit-torque magnetic random access memory.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Security Threats and Countermeasures in Three-Dimensional Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors.

[BibT_eX]

[DOI]

Kaisheng Ma

Xueqing Li

Yongpan Liu

John Sampson

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Building energy-efficient multi-level cell STT-RAM caches with data compression.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Computation-oriented fault-tolerance schemes for RRAM computing systems.

[BibT_eX]

[DOI]

Yu Wang

Huazhong Yang

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

POSTER: Bridge the Gap Between Neural Networks and Neuromorphic Hardware.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016

Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

TSocket: Thermal Sustainable Power Budgeting.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Adapting B+ -Tree for Emerging Nonvolatile Memory-Based Main Memory.

[BibT_eX]

[DOI]

Ping Chi

Wang-Chien Lee

John (Jack) Morgan Sampson

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power.

[BibT_eX]

[DOI]

IEEE Micro, 2016

BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2016

CNNLab: a Novel Parallel Framework for Neural Networks using GPU and FPGA-a Practical Study with Trade-off Analysis.

[BibT_eX]

[DOI]

CoRR, 2016

Redesigning software and systems for non-volatile processors on self-powered devices.

[BibT_eX]

[DOI]

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor.

[BibT_eX]

[DOI]

Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

A unified memory network architecture for in-memory computing in commodity servers.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Cambricon: An Instruction Set Architecture for Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Thermal-aware 3D design for side-channel information leakage.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Scalable memory fabric for silicon interposer-based multi-core systems.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

MNSIM: Simulation platform for memristor-based neuromorphic computing system.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

NVSim-VXs: an improved NVSim for variation aware STT-RAM simulation.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Neural network transformation under hardware constraints.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Compilers, 2016

Architecture design with STT-RAM: Opportunities and challenges.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Die-stacking Architecture

[BibT_eX]

[DOI]

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01747-6, 2015

Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference.

[BibT_eX]

[DOI]

Hsiang-Yun Cheng

ACM Trans. Design Autom. Electr. Syst., 2015

Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems.

[BibT_eX]

[DOI]

R. Iris Bahar

Alex K. Jones

John (Jack) Morgan Sampson

ACM Trans. Design Autom. Electr. Syst., 2015

Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2015

Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2015

EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2015

Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications.

[BibT_eX]

[DOI]

IEEE Micro, 2015

A Write-Aware STTRAM-Based Register File Architecture for GPGPU.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2015

Memory and Storage System Design with Nonvolatile Memory Technologies.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2015

NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2015

Leveraging nonvolatility for architecture design with emerging NVM.

[BibT_eX]

[DOI]

Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing.

[BibT_eX]

[DOI]

Kaisheng Ma

Nandhini Chandramoorthy

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Exploring memory controller configurations for many-core systems with 3D stacked DRAMs.

[BibT_eX]

[DOI]

Fen Ge

Jia Zhan

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures.

[BibT_eX]

[DOI]

Proceedings of the 29th ACM on International Conference on Supercomputing, 2015

Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Overcoming the challenges of crossbar resistive memory architectures.

[BibT_eX]

[DOI]

Naveen Muralimanohar

Rajeev Balasubramonian

Shimeng Yu

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Architecture exploration for ambient energy harvesting nonvolatile processors.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Energy Efficient RRAM Spiking Neural Network for Real Time Classification.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

DESTINY: a tool for modeling emerging 3D NVM and eDRAM caches.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

DimNoC: a dim silicon approach towards power-efficient on-chip network.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Ambient energy harvesting nonvolatile processors: from circuit to system.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Core vs. uncore: the heart of darkness.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Self-powered wearable sensor node: Challenges and opportunities.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Compilers, 2015

Heterogeneous architecture design with emerging 3D and non-volatile memory technologies.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues.

[BibT_eX]

[DOI]

Yang Zheng

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Nonvolatile memory allocation and hierarchy optimization for high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond.

[BibT_eX]

[DOI]

Naehyuck Chang

David Z. Pan

ACM Trans. Design Autom. Electr. Syst., 2014

Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Endurance-aware cache line management for non-volatile caches.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2014

Building and Optimizing MRAM-Based Commodity Memories.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2014

Preventing STT-RAM Last-Level Caches from Port Obstruction.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2014

Testable cross-power domain interface (CPDI) circuit design in monolithic 3D technology.

[BibT_eX]

[DOI]

Yang Du

ACM J. Emerg. Technol. Comput. Syst., 2014

On-Chip Hybrid Power Supply System for Wireless Sensor Nodes.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2014

An Embedded Co-AdaBoost based construction of software document relation coupled resource spaces for cyber-physical society.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2014

Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects.

[BibT_eX]

[DOI]

IEEE Des. Test, 2014

Compact models and model standard for 2.5D and 3D integration.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems.

[BibT_eX]

[DOI]

Onur Mutlu

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Efficient region-aware P/G TSV planning for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Enabling high-performance LPDDRx-compatible MRAM.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Making B+-tree efficient in PCM-based main memory.

[BibT_eX]

[DOI]

Ping Chi

Wang-Chien Lee

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

ProactiveDRAM: A DRAM-initiated retention management scheme.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Architecting 3D vertical resistive memory for next-generation storage systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Adaptive placement and migration policy for an STT-RAM-based hybrid cache.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

TSV power supply array electromigration lifetime analysis in 3D ICS.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

3D-SWIFT: a high-performance 3D-stacked wide IO DRAM.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Reliability-aware cross-point resistive memory design.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era.

[BibT_eX]

[DOI]

Jia Zhan

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Thermal-Sustainable Power Budgeting for Dynamic Threading.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

SwimmingLane: A composite approach to mitigate voltage droop effects in 3D power delivery network.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Designing vertical bandwidth reconfigurable 3D NoCs for many core systems.

[BibT_eX]

[DOI]

Proceedings of the 2014 International 3D Systems Integration Conference, 2014

A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests.

[BibT_eX]

[DOI]

Matt Poremba

Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013

Guest Editorial.

[BibT_eX]

[DOI]

Gabriel H. Loh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

WADE: Writeback-aware dynamic cache management for NVM-based main memory system.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2013

A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2013

Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs.

[BibT_eX]

[DOI]

Integr., 2013

Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2013

Assessment of Circuit Optimization Techniques Under NBTI.

[BibT_eX]

[DOI]

IEEE Des. Test, 2013

Kiln: closing the performance gap between systems with and without persistence support.

[BibT_eX]

[DOI]

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Cost-driven 3D design optimization with metal layer reduction technique.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

CPDI: Cross-power-domain interface circuit design in monolithic 3D technology.

[BibT_eX]

[DOI]

Yang Du

Proceedings of the International Symposium on Quality Electronic Design, 2013

TSV-aware topology generation for 3D Clock Tree Synthesis.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Designing scratchpad memory architecture with emerging STT-RAM memory technologies.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Low power multi-level-cell resistive memory design with incomplete data mapping.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Design of cross-point metal-oxide ReRAM emphasizing reliability and cost.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network.

[BibT_eX]

[DOI]

Yuan-Ying Chang

Yoshi Shih-Chieh Huang

Chung-Ta King

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

Thermomechanical stress-aware management for 3D IC designs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Future memory and interconnect technologies.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

OAP: an obstruction-aware cache management policy for STT-RAM last-level caches.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Designing energy-efficient NoC for real-time embedded systems through slack optimization.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Understanding the trade-offs in multi-level cell ReRAM memory design.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Low-Power Design of Emerging Memory Technologies.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs.

[BibT_eX]

[DOI]

Huazhong Yang

ACM Trans. Design Autom. Electr. Syst., 2012

Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling.

[BibT_eX]

[DOI]

Pallav Gupta

Marilyn Wolf

Dimitrios N. Serpanos

ACM Trans. Embed. Comput. Syst., 2012

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/Vdd Library and Device Sizing.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2012

ESL Design Methodology.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2012

An Embedded Co-AdaBoost and Its Application in Classification of Software Document Relation.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Conference on Semantics, Knowledge and Grids, 2012

MAGE: adaptive granularity and ECC for resilient and power efficient memory systems.

[BibT_eX]

[DOI]

Proceedings of the SC Conference on High Performance Computing Networking, 2012

NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Energy-efficient GPU design with reconfigurable in-package graphics memory.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Design trade-offs for high density cross-point resistive memory.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Optimizing bandwidth and power of graphics memory with hybrid memory technologies and adaptive data migration.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Mitigating electromigration of power supply networks using bidirectional current stress.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Modeling and design exploration of FBDRAM as on-chip memory.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Point and discard: a hard-error-tolerant architecture for non-volatile last level caches.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs.

[BibT_eX]

[DOI]

Ravishankar R. Iyer

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs.

[BibT_eX]

[DOI]

Yu Wang

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Low power memristor-based ReRAM design with Error Correcting Code.

[BibT_eX]

[DOI]

Yang Xiao

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Thermal-aware power network design for IR drop reduction in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Influence of Stacked 3D Memory/Cache Architectures on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2011

Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2011

Variation-Aware Task and Communication Mapping for MPSoC Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Hybrid checkpointing using emerging nonvolatile memories for future exascale systems.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2011

Editorial- three-dimensional integrated circuits design.

[BibT_eX]

[DOI]

Pol Marchal

IET Comput. Digit. Tech., 2011

Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2011

Three-dimensional Integrated Circuits: Design, EDA, and Architecture.

[BibT_eX]

[DOI]

Found. Trends Electron. Des. Autom., 2011

Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Modeling, Architecture, and Applications for Emerging Memory Technologies.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2011

Impact of Circuit Degradation on FPGA Design Security.

[BibT_eX]

[DOI]

Han-Wei Chen

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Moguls: a model to explore the memory hierarchy for bandwidth improvements.

[BibT_eX]

[DOI]

Christopher J. Hughes

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs.

[BibT_eX]

[DOI]

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

F2BFLY: an on-chip free-space optical network with wavelength-switching.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Energy-efficient multi-level cell phase-change memory system with data encoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Bandwidth-aware reconfigurable cache design with hybrid memory technologies.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Device-architecture co-optimization of STT-RAM based memory for low power embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Enabling architectural innovations using non-volatile memory.

[BibT_eX]

[DOI]

Vinay Saripalli

Karthik Swaminathan

Ravindhiran Mukundrajan

Suman Datta

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

An energy-efficient 3D CMP design with fine-grained voltage scaling.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Design implications of memristor-based RRAM cross-point structures.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Automated mapping for reconfigurable single-electron transistor arrays.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

System-level design space exploration for three-dimensional (3D) SoCs.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

A frequent-value based PRAM memory architecture.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Enabling quality-of-service in nanophotonic network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

On-chip hybrid power supply system for wireless sensor nodes.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

AdaMS: Adaptive MLC/SLC phase-change memory design for file storage.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Total Power Optimization for Combinational Logic Using Genetic Algorithms.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2010

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Design exploration of hybrid caches with disparate memory technologies.

[BibT_eX]

[DOI]

Ramakrishnan Rajamony

ACM Trans. Archit. Code Optim., 2010

Test-access mechanism optimization for core-based three-dimensional SOCs.

[BibT_eX]

[DOI]

Microelectron. J., 2010

3D Stacked Microprocessor: Are We There Yet?

[BibT_eX]

[DOI]

Gabriel H. Loh

IEEE Micro, 2010

Processor Architecture Design Using 3D Integration Technology.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support.

[BibT_eX]

[DOI]

Proceedings of the Conference on High Performance Computing Networking, 2010

LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support.

[BibT_eX]

[DOI]

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Modeling TSV open defects in 3D-stacked DRAM.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Low-power dual-element memristor based memory design.

[BibT_eX]

[DOI]

Yiran Chen

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Energy- and endurance-aware design of phase change memory caches.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Cost-aware three-dimensional (3D) many-core multiprocessor design.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Cost-driven 3D integration with interconnect layers.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Impact of process variations on emerging memristor.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

A customized design of DRAM controller for on-chip 3D DRAM stacking.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Energy and performance driven circuit design for emerging phase-change memory.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Architectural benefits and design challenges for three-dimensional integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

A 3D SoC design for H.264 application with on-chip DRAM stacking.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on 3D System Integration, 2010

3D memory stacking for fast checkpointing/restore applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits.

[BibT_eX]

[DOI]

Rajaraman Ramanarayanan

Jungsub Kim

Kenan Unlu

IEEE Trans. Dependable Secur. Comput., 2009

Process-Variation-Aware Adaptive Cache Architecture and Management.

[BibT_eX]

[DOI]

Madhu Mutyam

IEEE Trans. Computers, 2009

Scan-chain design and optimization for three-dimensional integrated circuits.

[BibT_eX]

[DOI]

Paul Falkenstern

ACM J. Emerg. Technol. Comput. Syst., 2009

New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components.

[BibT_eX]

[DOI]

Michael DeBole

Int. J. Parallel Program., 2009

Temperature-Aware NBTI Modeling Techniques in Digital Circuits.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2009

Statistical High-Level Synthesis under Process Variability.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2009

Guest Editors' Introduction: Opportunities and Challenges of 3D Integration.

[BibT_eX]

[DOI]

David S. Kung

IEEE Des. Test Comput., 2009

Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

Networks-on-chip in emerging interconnect paradigms: Advantages and challenges.

[BibT_eX]

[DOI]

Luca P. Carloni

Partha Pande

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.

[BibT_eX]

[DOI]

Soumya Eachempati

Aditya Yanamandra

Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

NBTI-aware statistical circuit delay assessment.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Exploration of 3D stacked L2 cache design for high performance and efficient thermal control.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Emerging technologies and their impact on system design.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Hybrid cache architecture with disparate memory technologies.

[BibT_eX]

[DOI]

Ramakrishnan Rajamony

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs.

[BibT_eX]

[DOI]

Brandon Noia

Proceedings of the 27th International Conference on Computer Design, 2009

3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Design, 2009

Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning.

[BibT_eX]

[DOI]

Balaji Vaidyanathan

Anthony S. Oates

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A novel architecture of the 3D stacked MRAM L2 cache for CMPs.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Power and performance of read-write aware Hybrid Caches with non-volatile memories.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Gate replacement techniques for simultaneous leakage and aging optimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

CheckerCore: enhancing an FPGA soft core to capture worst-case execution times.

[BibT_eX]

[DOI]

Raghuveer Raghavendra

Proceedings of the 2009 International Conference on Compilers, 2009

Variation-aware resource sharing and binding in behavioral synthesis.

[BibT_eX]

[DOI]

Andrés Takach

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A criticality-driven microarchitectural three dimensional (3D) floorplanner.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs).

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A framework for estimating NBTI degradation of microarchitectural components.

[BibT_eX]

[DOI]

Michael DeBole

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Tolerating process variations in high-level synthesis using transparent latches.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC).

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on 3D System Integration, 2009

Arithmetic unit design using 180nm TSV-based 3D stacking technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on 3D System Integration, 2009

Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs.

[BibT_eX]

[DOI]

Brent Hollosi

Ravi Sankar Parameswaran Nair

Jia Di

Scott C. Smith

Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008

Case Study of Reliability-Aware and Low-Power Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Design Space Exploration for 3-D Cache.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Toward Increasing FPGA Lifetime.

[BibT_eX]

[DOI]

Karthik Sarpatwari

IEEE Trans. Dependable Secur. Comput., 2008

Editorial: Special issue on 3D integrated circuits and microarchitectures.

[BibT_eX]

[DOI]

Jason Cong

Paul D. Franzon

ACM J. Emerg. Technol. Comput. Syst., 2008

Power optimization for FinFET-based circuits using genetic algorithms.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

ILP-based scheme for timing variation-aware scheduling and resource binding.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Two-dimensional crosstalk avoidance codes.

[BibT_eX]

[DOI]

Xuebin Wu

Zhiyuan Yan

Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Thermal-aware Design Considerations for Application-Specific Instruction Set Processor.

[BibT_eX]

[DOI]

Anand Sivasubramaniam

Proceedings of the IEEE Symposium on Application Specific Processors, 2008

Test-Access Solutions for Three-Dimensional SOCs.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Hierarchical Soft Error Estimation Tool (HSEET).

[BibT_eX]

[DOI]

R. Rajaraman

Kenan Unlu

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

MIRA: A Multi-layered On-Chip Interconnect Router Architecture.

[BibT_eX]

[DOI]

Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Comparative analysis of NBTI effects on low power and high performance flip-flops.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

Thermal-aware reliability analysis for platform FPGAs.

[BibT_eX]

[DOI]

Sungmin Bae

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A low-power phase change memory based hybrid cache architecture.

[BibT_eX]

[DOI]

Karthik Sarpatwari

Aditya Yanamandra

Osama Awadel Karim

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Technology, CAD tools, and designs for emerging 3D integration technology.

[BibT_eX]

[DOI]

Syed M. Alam

Mike Ignatowski

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A Variation Aware High Level Synthesis Framework.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Variability-driven module selection with joint design time optimization and post-silicon tuning.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Reliability-aware Co-synthesis for Embedded Systems.

[BibT_eX]

[DOI]

Lin Li

J. VLSI Signal Process., 2007

Code Decompression Unit Design for VLIW Embedded Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Code Compression for VLIW Embedded Systems Using a Self-Generating Table.

[BibT_eX]

[DOI]

Chang Hong Lin

IEEE Trans. Very Large Scale Integr. Syst., 2007

Processor Design in 3D Die-Stacking Technologies.

[BibT_eX]

[DOI]

Gabriel H. Loh

Bryan Black

IEEE Micro, 2007

On-chip bus thermal analysis and optimisation.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Architecting Microprocessor Components in 3D Design Space.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Collaborative VLSI-CAD Instruction in the Digital Sandbox.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Variation Impact on SER of Combinational Circuits.

[BibT_eX]

[DOI]

R. Rajaraman

Sivaprakasam Suresh

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Variation Analysis of CAM Cells.

[BibT_eX]

[DOI]

Amol Mupid

Madhu Mutyam

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Modeling of PMOS NBTI Effect Considering Temperature Variation.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A novel dimensionally-decomposed router for on-chip communication in 3D architectures.

[BibT_eX]

[DOI]

Jongman Kim

Dongkook Park

Reetuparna Das

Mazin S. Yousif

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Scan chain design for three-dimensional integrated circuits (3D ICs).

[BibT_eX]

[DOI]

Paul Falkenstern

Proceedings of the 25th International Conference on Computer Design, 2007

FPGA routing architecture analysis under variations.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

Variation-aware task allocation and scheduling for MPSoC.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Temperature-aware NBTI modeling and the impact of input vector control on performance degradation.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A novel criticality computation method in statistical timing analysis.

[BibT_eX]

[DOI]

Hai Ju

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2006

Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Design space exploration for 3D architectures.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2006

Reliability Concerns in Embedded System Designs.

[BibT_eX]

[DOI]

Computer, 2006

A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.

[BibT_eX]

[DOI]

Thomas D. Richardson

Dongkook Park

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

SEAT-LA: A Soft Error Analysis Tool for Combinational Logic.

[BibT_eX]

[DOI]

R. Rajaraman

Jungsub Kim

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression.

[BibT_eX]

[DOI]

Balaji Vaidyanathan

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Modeling the Impact of Process Variation on Critical Charge Distribution.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Reliability-Aware SOC Voltage Islands Partition and Floorplan.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Dependability Analysis of Nano-scale FinFET circuits.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Delay and Energy Efficient Data Transmission for On-Chip Buses.

[BibT_eX]

[DOI]

Madhu Mutyam

Melvin Eze

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Interconnect and Thermal-aware Floorplanning for 3D Microprocessors.

[BibT_eX]

[DOI]

Greg M. Link

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Design and Management of 3D Chip Multiprocessors Using Network-in-Memory.

[BibT_eX]

[DOI]

Feihui Li

Thomas D. Richardson

Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Guaranteeing performance yield in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

On-chip bus thermal analysis and optimization.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

FLAW: FPGA lifetime awareness.

[BibT_eX]

[DOI]

Karthik Sarpatwari

Proceedings of the 43rd Design Automation Conference, 2006

Optimal topology exploration for application-specific 3D architectures.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Leakage Optimized DECAP Design for FPGAs.

[BibT_eX]

[DOI]

Balaji Vaidyanathan

Rong Luo

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits.

[BibT_eX]

[DOI]

Wenping Wang

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters.

[BibT_eX]

[DOI]

Daniel Hostetler

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

An ILP Formulation for Reliability-Oriented High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Reliability-Centric Hardware/Software Co-Design.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Thermal-Aware Floorplanning Using Genetic Algorithms.

[BibT_eX]

[DOI]

Charles Addo-Quaye

Theo Theocharides

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Three-Dimensional Cache Design Exploration Using 3DCacti.

[BibT_eX]

[DOI]

Sri Hari Krishna Narayanan

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Temperature-Sensitive Loop Parallelization for Chip Multiprocessors.

[BibT_eX]

[DOI]

Guilin Chen

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Temperature-Aware Voltage Islands Architecting in System-on-Chip Design.

[BibT_eX]

[DOI]

Greg M. Link

Nagu R. Dhanwada

John Conner

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach.

[BibT_eX]

[DOI]

Dimitrios N. Serpanos

Proceedings of the 2005 Design, 2005

Leakage-Aware Interconnect for On-Chip Network.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Reliability-Centric High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Thermal-Aware Task Allocation and Scheduling for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Low-leakage robust SRAM cell design for sub-100nm technologies.

[BibT_eX]

[DOI]

Wenping Wang

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Designing reliable circuit in the presence of soft errors.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

The Effect of Threshold Voltages on the Soft Error Rate.

[BibT_eX]

[DOI]

Rajaraman Ramanarayanan

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Improving soft-error tolerance of FPGA configuration bits.

[BibT_eX]

[DOI]

Aman Gayasen

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Design of a nanosensor array architecture.

[BibT_eX]

[DOI]

Wei Xu

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

LZW-Based Code Compression for VLIW Embedded Systems.

[BibT_eX]

[DOI]

Chang Hong Lin

Proceedings of the 2004 Design, 2004

2003

Augmenting Platform-Based Design with Synthesis Tools.

[BibT_eX]

[DOI]

Jiang Xu

J. Circuits Syst. Comput., 2003

Effect of Power Optimizations on Soft Error Rate.

[BibT_eX]

[DOI]

Rajaraman Ramanarayanan

Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Code Compression Using Variable-to-fixed Coding Based on Arithmetic Coding.

[BibT_eX]

[DOI]

Proceedings of the 2003 Data Compression Conference (DCC 2003), 2003

Profile-Driven Selective Code Compression.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

2002

Code Compression for VLIW Processors Using Variable-to-Fixed Coding.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

2001

A code decompression architecture for VLIW processors.

[BibT_eX]

[DOI]

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Code Compression for VLIW Processors.

[BibT_eX]

[DOI]

Proceedings of the Data Compression Conference, 2001

Allocation and scheduling of conditional task graph in hardware/software co-synthesis.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Co-synthesis with custom ASICs.

[BibT_eX]

[DOI]