Yuan-Shin Hwang

Proceedings of the 52nd International Conference on Parallel Processing Workshops, 2023

2021

Pointer-Based Divergence Analysis for OpenCL 2.0 Programs.

[BibT_eX]

[DOI]

ACM Trans. Parallel Comput., 2021

2020

A framework for scheduling dependent programs on GPU architectures.

[BibT_eX]

[DOI]

J. Syst. Archit., 2020

2019

Support OpenCL 2.0 Compiler on LLVM for PTX Simulators.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2019

GPUBlocks: GUI Programming Tool for CUDA and OpenCL.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2019

Devise Rust Compiler Optimizations on RISC-V Architectures with SIMD Instructions.

[BibT_eX]

[DOI]

Proceedings of the 48th International Conference on Parallel Processing, 2019

2018

Architecture and Compiler Support for GPUs Using Energy-Efficient Affine Register Files.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

Scheduling Methods to Optimize Dependent Programs for GPU Architecture.

[BibT_eX]

[DOI]

Proceedings of the 47th International Conference on Parallel Processing, 2018

Graph Support and Scheduling for OpenCL on Heterogeneous Multi-core Systems.

[BibT_eX]

[DOI]

Proceedings of the 47th International Conference on Parallel Processing, 2018

2017

Floating accumulator architecture.

[BibT_eX]

[DOI]

Wei-Che Hsu

Microprocess. Microsystems, 2017

Enabling PoCL-based runtime frameworks on the HSA for OpenCL 2.0 support.

[BibT_eX]

[DOI]

J. Syst. Archit., 2017

Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

OpenCL 2.0 Compiler Adaptation on LLVM for PTX Simulators.

[BibT_eX]

[DOI]

Proceedings of the 46th International Conference on Parallel Processing Workshops, 2017

2016

Energy Efficient Affine Register File for GPU Microarchitecture.

[BibT_eX]

[DOI]

Proceedings of the 45th International Conference on Parallel Processing Workshops, 2016

2015

CUDABlock: A GUI Programming Tool for CUDA.

[BibT_eX]

[DOI]

Hsih-Hsin Lin

Chia-Heng Tu

Proceedings of the 44th International Conference on Parallel Processing Workshops, 2015

2012

Support of Probabilistic Pointer Analysis in the SSA Form.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2012

Doubling the number of registers on ARM processors.

[BibT_eX]

[DOI]

Hsu-Hung Chiang

Huang-Jia Cheng

Proceedings of the 16th Workshop on Interaction between Compilers and Computer Architectures, 2012

2010

DisIRer: Converting a retargetable compiler into a multiplatform binary translator.

[BibT_eX]

[DOI]

Tzong-Yen Lin

Rong-Guey Chang

ACM Trans. Archit. Code Optim., 2010

On reducing load/store latencies of cache accesses.

[BibT_eX]

[DOI]

J. Syst. Archit., 2010

Trading Conditional Execution for More Registers on ARM Processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010

2009

Indirect-Mapped Caches: Approximating Set-Associativity with Direct-Mapped Caches.

[BibT_eX]

Proceedings of the 2009 International Conference on Computer Design, 2009

2007

Snug set-associative caches: Reducing leakage power of instruction and data caches with no performance penalties.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2007

2006

Dynamic Load-Balancing of Jini and .NET Services.

[BibT_eX]

[DOI]

Ying Chen Lin

Sy-Yuan Li

Proceedings of the 2006 International Conference on Parallel Processing Workshops (ICPP Workshops 2006), 2006

2005

Dynamic Load-Balancing of Jini Services with Smart Proxies.

[BibT_eX]

Hung-Hsiang Lin

Chia-Heng Tu

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2005

Snug set-associative caches: reducing leakage power while improving performance.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Minimal Steiner Trees in X Architecture with Obstacles.

[BibT_eX]

Chung-Chin Luo

Gene Eu Jan

Proceedings of the 2005 International Conference on Computer Design, 2005

2004

Interprocedural Probabilistic Pointer Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2004

Novel Hierarchical Interconnection Networks for High-Performance Multicomputer Systems.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2004

Hierarchical Interconnection Networks Based on (3, 3)-Graphs for Massively Parallel Processors.

[BibT_eX]

[DOI]

Gene Eu Jan

IEICE Trans. Inf. Syst., 2004

2003

An Efficient Algorithm for Perfect Load Balancing on Hypercube Multiprocessors.

[BibT_eX]

[DOI]

Gene Eu Jan

J. Supercomput., 2003

Interprocedural definition-use chains of dynamic pointer-linked data structures.

[BibT_eX]

[DOI]

Sci. Program., 2003

Identifying parallelism in programs with cyclic graphs.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2003

Compiler support for speculative multithreading architecture with probabilistic points-to analysis.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2003

2002

Parallelizing graph construction operations in programs with cyclic graphs.

[BibT_eX]

[DOI]

Parallel Comput., 2002

Compiler Optimizations with DSP-Specific Semantic Descriptions.

[BibT_eX]

[DOI]

Yung-Chia Lin

Jenq Kuen Lee

Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002

2001

Probabilistic Points-to Analysis.

[BibT_eX]

[DOI]

Proceedings of the Languages and Compilers for Parallel Computing, 2001

Runtime and Compiler Support for Irregular Computations.

[BibT_eX]

[DOI]

Proceedings of the Compiler Optimizations for Scalable Parallel Systems Languages, 2001

1997

Programming Irregular Applications: Runtime Support, Compilation and Tools.

[BibT_eX]

[DOI]

Adv. Comput., 1997

Identifying DEF/USE Information of Statements that Construct and Traverse Dynamic Recursive Data Structures.

[BibT_eX]

[DOI]

Proceedings of the Languages and Compilers for Parallel Computing, 1997

1996

Side Effect Analysis on User-Defined Reduction Functions with Dynamic Pointer-Linked Data Structures.

[BibT_eX]

[DOI]