Yuan-Kai Ho

According to our database, Yuan-Kai Ho authored at least 7 papers between 2008 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2014

Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs.

Yuan-Kai Ho, Hsu-Chieh Lee, Webber Lee, Yao-Wen Chang, Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013

Escape Routing for Staggered-Pin-Array PCBs.

Yuan-Kai Ho, Hsu-Chieh Lee, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Multiple chip planning for chip-interposer codesign.

Yuan-Kai Ho, Yao-Wen Chang

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Layer minimization in escape routing for staggered-pin-array PCBs.

Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Obstacle-avoiding free-assignment routing for flip-chip designs.

Po-Wei Lee, Hsu-Chieh Lee, Yuan-Kai Ho, Yao-Wen Chang, Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2010

Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization.

Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2008

Type-matching clock tree for zero skew clock gating.

Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu

Proceedings of the 45th Design Automation Conference, 2008