Yuan-Chun Luo
Orcid: 0000-0001-5793-075X
According to our database1,
Yuan-Chun Luo
authored at least 16 papers
between 2018 and 2024.
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Bibliography
2024
Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads.
IEEE Trans. Very Large Scale Integr. Syst., September, 2024
Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture.
IEEE Trans. Very Large Scale Integr. Syst., September, 2024
Engineering nvCap From FEOL to BEOL with Ferroelectric Small-signal Non-destructive Read.
Proceedings of the IEEE International Memory Workshop, 2024
Digital CIM with Noisy SRAM Bit: A Compact Clustered Annealer for Large-Scale Combinatorial Optimization.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
Scalable In-Memory Clustered Annealer With Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
Proceedings of the IEEE International Reliability Physics Symposium, 2023
2022
Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Ferroelectric-Based Volatile/Non-Volatile Dual-Mode Buffer Memory for Deep Neural Network Accelerators.
IEEE Trans. Computers, 2022
Adv. Intell. Syst., 2022
2021
Proceedings of the IEEE International Memory Workshop, 2021
Proceedings of the IEEE International Memory Workshop, 2021
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
A FeRAM based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Proceedings of the 2020 Device Research Conference, 2020
2018
DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout.
Proceedings of the 2018 International Symposium on VLSI Design, 2018