Yu Wang

Orcid: 0000-0002-5561-4435

Affiliations:

Nanjing Xiaozhuang University, School of Electronics Engineering, China

According to our database¹, Yu Wang authored at least 9 papers between 2021 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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Bibliography

2024

FDM: Fused Double-Multiply Design for Low-Latency and Area- and Power-Efficient Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

An Optimized Architecture for Computing the Square Root of Complex Numbers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2022

High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

ML-PLAC: Multiplierless Piecewise Linear Approximation for Nonlinear Function Evaluation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A New Design of a CMOS Vertical Hall Sensor with a Low Offset.

[BibT_eX]

[DOI]

Sensors, 2022

An optimized hardware implementation of the CORDIC algorithm.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2022

Reconfigurable Multifunction Computing Unit Using an Universal Piecewise Linear Method.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Yu Wang

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