Yu-Tsun Chien

According to our database, Yu-Tsun Chien authored at least 6 papers between 1999 and 2005.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2005

Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters.

Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee

Proceedings of the 2005 Design, 2005

2002

Design of an Inter-plane Circuit for Clocked PLAs.

Chua-Chin Wang, Ya-Hsin Hsueh, Yu-Tsun Chien, Ying-Pei Chen

VLSI Design, 2002

2001

Pattern Recognitin by High-Capacity Polynomial Bidirectional Hetero-Associative Network.

Chua-Chin Wang, Cheng-Fa Tsai, Yu-Tsun Chien

J. Inf. Sci. Eng., 2001

2000

A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop.

Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen

VLSI Design, 2000

Design of an inter-plane circuit for clocked PLAs.

Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop.

Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999