Yu-Tang Lin
According to our database1,
Yu-Tang Lin
authored at least 3 papers
between 2021 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Multi-Gate Access Transistor to Minimize GIDL Leakage Current for Scaling 2-tier Stacked 4F<sup>2</sup> DRAM Below Equivalent 10nm Node.
Proceedings of the IEEE International Memory Workshop, 2024
Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two Asymmetrical Horizontal WL's and Vertical BL for Better Cell Size Scaling and Array Selection.
Proceedings of the IEEE International Memory Workshop, 2024
2021
Sensors, 2021