Yu-Sian Lu

According to our database¹, Yu-Sian Lu authored at least 2 papers between 2021 and 2024.

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2024

A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2024

2021

A 10 GHz Dual-Loop PLL with Active Noise Cancellation Achieving 12dB Spur and 29% Noise Reduction.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021