Yu-Shih Su

According to our database¹, Yu-Shih Su authored at least 9 papers between 2007 and 2013.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2013

Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Benchmarking for research in power delivery networks of three-dimensional integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2013

2012

Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Performance Optimization Using Variable-Latency Design Style.

[BibT_eX]

[DOI]

Yu-Shih Su

Da-Chung Wang

Shih-Chieh Chang

Malgorzata Marek-Sadowska

IEEE Trans. Very Large Scale Integr. Syst., 2011

Fault-tolerant 3D clock network.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009

Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008

Synthesis of a novel timing-error detection architecture.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

2007

An Efficient Mechanism for Performance Optimization of Variable-Latency Designs.

[BibT_eX]

[DOI]

Yu-Shih Su

Da-Chung Wang

Shih-Chieh Chang

Malgorzata Marek-Sadowska

Proceedings of the 44th Design Automation Conference, 2007

Yu-Shih Su

Timeline

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Links

On csauthors.net:

Bibliography

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