Yu-Nan Shih

According to our database, Yu-Nan Shih authored at least 3 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET.

Wei-Chih Chen, Shu-Chun Yang, Yu-Nan Shih, Wen-Hung Huang, Chien-Chun Tsai, Kenny Cheng-Hsiang Hsieh

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2012

A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology.

Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee

IEEE J. Solid State Circuits, 2012

2011

A 40Gb/s TX and RX chip set in 65nm CMOS.

Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee

Proceedings of the IEEE International Solid-State Circuits Conference, 2011