Yu-Lung Lo
Orcid: 0000-0003-2440-9778
According to our database1,
Yu-Lung Lo
authored at least 36 papers
between 2002 and 2024.
Collaborative distances:
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Bibliography
2024
A Hierarchical Tree-Structured Control Digital Low Drop-out Regulator with Status-Dumping Mechanism.
Proceedings of the 21st International SoC Design Conference, 2024
Proceedings of the 21st International SoC Design Conference, 2024
2023
Intelligent Additive Manufacturing Architecture for Enhancing Uniformity of Surface Roughness and Mechanical Properties of Laser Powder Bed Fusion Components.
IEEE Trans Autom. Sci. Eng., October, 2023
Characterization of Mean Absorbance of Anisotropic Turbid Media Using Stokes-Mueller Matrix Polarimetry Approach.
IEEE Trans. Instrum. Meas., 2023
2022
Fiber-Based Triboelectric Nanogenerator for Mechanical Energy Harvesting and Its Application to a Human-Machine Interface.
Sensors, 2022
2019
An Approach to Measure Tilt Motion, Straightness and Position of Precision Linear Stage with a 3D Sinusoidal-Groove Linear Reflective Grating and Triangular Wave-Based Subdivision Method.
Sensors, 2019
IEEE Robotics Autom. Lett., 2019
2018
Proceedings of the 6th International Conference on Photonics, Optics and Laser Technology, 2018
2017
Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input.
Circuits Syst. Signal Process., 2017
A Low-Voltage PLL Design Using a New Calibration Technique for Low-Power Implantable Biomedical Systems.
Circuits Syst. Signal Process., 2017
A High-Efficiency CMOS Rectifier with Wide Harvesting Range and Wide Band Based on MPPT Technique for Low-Power IoT System Applications.
Circuits Syst. Signal Process., 2017
2015
Analysis and design considerations of static CMOS logics under process, voltage and temperature variation in UMC 0.18µm CMOS process.
Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015
2013
A low-area full-division-range programmable frequency divider with a 50% duty-cycle output.
Microelectron. J., 2013
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
2012
A 0.7 V input output-capacitor-free digitally controlled low-dropout regulator with high current efficiency in 0.35 μm CMOS technology.
Microelectron. J., 2012
A 50 ns Verify Speed in Resistive Random Access Memory by Using a Write Resistance Tracking Circuit.
IEICE Trans. Electron., 2012
2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
2010
IEICE Trans. Electron., 2010
2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
J. Convergence Inf. Technol., 2009
IEICE Trans. Electron., 2009
Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
2007
A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
2004
A fast-lock DLL with power-on reset circuit.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
Wirebond profiles characterized by a modified linkage-spring model which includes a looping speed factor.
Microelectron. Reliab., 2002