Yu-Lin Deng

According to our database, Yu-Lin Deng authored at least 2 papers between 2019 and 2020.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2020

2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations.

Chua-Chin Wang, Zong-You Hou, Yu-Lin Deng, U. Fat Chio, Wei Wang

J. Circuits Syst. Comput., 2020

2019

500 MHz 90 nm CMOS 2 \(\times \) VDD Digital Output Buffer Immunity to Process and Voltage Variations.

Chua-Chin Wang, Tsung-Yi Tsai, Yu-Lin Deng, Tzung-Je Lee

Circuits Syst. Signal Process., 2019