Yu-Juey Chang

According to our database¹, Yu-Juey Chang authored at least 3 papers between 2006 and 2011.

Collaborative distances:

Timeline

Book

In proceedings

Article

PhD thesis

Dataset

Other

2011

Design of High-Performance CMOS Level Converters Considering PVT Variations.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2011

2010

Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2010

2006

Design of STR level converters for SoCs using the multi-island dual-VDD design technique.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006