Yu Ji

Orcid: 0000-0001-7751-1827

Affiliations:

University of California Santa Barbara, CA, USA
Tsinghua University, Department of Computer Science and Technology, Beijing, China (PhD 2020)

According to our database¹, Yu Ji authored at least 20 papers between 2016 and 2022.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

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In proceedings

Article

PhD thesis

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Other

Bibliography

2022

A Systematic View of Model Leakage Risks in Deep Neural Network Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

2021

A Reduced Architecture for ReRAM-Based Neural Network Accelerator and Its Software Stack.

[BibT_eX]

[DOI]

Yu Ji

Zixin Liu

Youhui Zhang

IEEE Trans. Computers, 2021

2020

NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2020

DeepSniffer: A DNN Model Extraction Framework Based on Learning Architectural Hints.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019

Neural Network Model Extraction Attacks in Edge Devices by Hearing Architectural Hints.

[BibT_eX]

[DOI]

CoRR, 2019

QGAN: Quantized Generative Adversarial Networks.

[BibT_eX]

[DOI]

CoRR, 2019

Programmable Neural Network Trojan for Pre-Trained Feature Extractor.

[BibT_eX]

[DOI]

CoRR, 2019

NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2019

Memory Trojan Attack on Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018

Bridging the Gap Between Neural Networks and Neuromorphic Hardware with A Neural Network Compiler.

[BibT_eX]

[DOI]

CoRR, 2018

Crossbar-Aware Neural Network Pruning.

[BibT_eX]

[DOI]

IEEE Access, 2018

TETRIS: TilE-matching the TRemendous Irregular Sparsity.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems 2018, 2018

SNrram: an efficient sparse neural network computation architecture based on resistive random-access memory.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

Bridge the Gap between Neural Networks and Neuromorphic Hardware with a Neural Network Compiler.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017

POSTER: Bridge the Gap Between Neural Networks and Neuromorphic Hardware.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016

Modelling Spiking Neural Network from the Architecture Evaluation Perspective.

[BibT_eX]

[DOI]

Yu Ji

Youhui Zhang

Weimin Zheng

J. Comput. Sci. Technol., 2016

NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Optimized Mapping Spiking Neural Networks onto Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Architectures for Parallel Processing, 2016

Neural network transformation under hardware constraints.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Compilers, 2016

Yu Ji

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