Yu-Jen Huang
According to our database1,
Yu-Jen Huang
authored at least 31 papers
between 2005 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2022
>100 Gbps 3×3 MIMO V-Band RoF System for up to 100 m Wireless Transmission Enabled by NN-based Equalization.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022
Mobile 14-GHz Bandwidth Fronthaul Link Supporting 128 RF-Chain Signals for 6G Ma-MIMO Beamforming.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022
2021
End-to-End Performance Optimization for Training Streaming Convolutional Neural Networks using Billion-Pixel Whole-Slide Images.
Proceedings of the 2021 IEEE International Conference on Big Data (Big Data), 2021
2020
Proceedings of the Pattern Recognition. ICPR International Workshops and Challenges, 2020
2014
ACM Trans. Embed. Comput. Syst., 2014
Proceedings of the 5th International Conference on Ambient Systems, 2014
2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
A Self-Repair Technique for Content Addressable Memories with Address-Input-Free Writing Function.
J. Inf. Sci. Eng., 2013
Proceedings of the 1st Symposium on Spatial User Interaction, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Low-Cost Self-Test Techniques for Small RAMs in SOCs Using Enhanced IEEE 1500 Test Wrappers.
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
2010
DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Testing Random Defect and Process Variation Induced Comparison Faults of TCAMs With Asymmetric Cells.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the 15th European Test Symposium, 2010
2009
IEEE Micro, 2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy.
J. Electron. Test., 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
2007
Some existence results for solutions of generalized vector quasi-equilibrium problems.
Math. Methods Oper. Res., 2007
Testing ternary content addressable memories with active neighbourhood pattern-sensitive faults.
IET Comput. Digit. Tech., 2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
2006
Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories.
Proceedings of the 11th European Test Symposium, 2006
A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
2005
A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005