Yu Hu

Affiliations:

Huazhong University of Science and Technology, School of Optical and Electronic Information, Department of Electronic Science and Technology, Wuhan, China (since 2012)
University of Alberta, Department of Electrical and Computer Engineering, Edmonton, Canada (2010 - 2012)
University of California at Los Angeles, Department of Electrical Engineering, CA, USA (PhD 2009)
Tsinghua University, Computer Science and Technology Department, Beijing, China (2002 - 2005)

According to our database¹, Yu Hu authored at least 56 papers between 2005 and 2021.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2021

Quantization of Deep Neural Networks for Accurate Edge Computing.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2021

Quantization of Deep Neural Networks for Accurate EdgeComputing.

[BibT_eX]

[DOI]

CoRR, 2021

2019

MDA: A Reconfigurable Memristor-Based Distance Accelerator for Time Series Mining on Data Centers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018

Accelerating Dynamic Time Warping With Memristor-Based Customized Fabrics.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Efficient Hardware Implementation of Cellular Neural Networks with Incremental Quantization and Early Exit.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2018

Scalable and Parameterized Architecture for Efficient Stream Mining.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Quantization of Fully Convolutional Networks for Accurate Biomedical Image Segmentation.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Conference on Computer Vision and Pattern Recognition, 2018

2017

Efficient hardware implementation of cellular neural networks with powers-of-two based incremental quantization.

[BibT_eX]

[DOI]

Proceedings of the Neuromorphic Computing Symposium, 2017

An Efficient Memristor-based Distance Accelerator for Time Series Data Mining on Data Centers.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Body-Earth Mover's Distance: A Matching-Based Approach for Sleep Posture Recognition.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2016

2015

A flexible control study of variable speed limit in connected vehicle systems.

[BibT_eX]

[DOI]

Int. J. Embed. Syst., 2015

Energy-efficient pipelined DTW architecture on hybrid embedded platforms.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

On-bed sleep posture recognition based on body-earth mover's distance.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2013

SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty.

[BibT_eX]

[DOI]

Integr., 2013

Fast Filter-Based Boolean Matchers.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2013

An energy-efficient sub-Nyquist sampling method based on compressed sensing in wireless sensor network for vehicle detection.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Connected Vehicles and Expo, 2013

A Simulation Study of Connected Vehicle Systems Using Named Data Networking.

[BibT_eX]

[DOI]

Proceedings of the Cloud Computing - 4th International Conference, CloudComp 2013, Wuhan, 2013

2011

In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

System-in-Package: Electrical and Layout Perspectives.

[BibT_eX]

[DOI]

Found. Trends Electron. Des. Autom., 2011

Enhancement of incremental design for FPGAs using circuit similarity.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Acceleration of Multi-agent Simulation on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

A method to build reconfigurable architectures by extracting common subgraphs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

Accelerating Boolean Matching Using Bloom Filter.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Engineering a scalable Boolean matching based on EDA SaaS 2.0.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

On power and fault-tolerance optimization in FPGA physical synthesis.

[BibT_eX]

[DOI]

Manu Jose

Yu Hu

Rupak Majumdar

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Accelerating FPGA design space exploration using circuit similarity-based placement.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

Building a faster boolean matcher using bloom filter.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Rewiring for robustness.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Fault-tolerant resynthesis with dual-output LUTs.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Worst case timing jitter and amplitude noise in differential signaling.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Simultaneous test pattern compaction, ordering and X-filling for testing power reduction.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

IPR: In-Place Reconfiguration for FPGA fault tolerance.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008

Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Dual-Vdd Buffer Insertion for Power Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Fashion: A Fast and Accurate Solution to Global Routing Problem.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A full-scale solution to the rectilinear obstacle-avoiding Steiner problem.

[BibT_eX]

[DOI]

Integr., 2008

Robust FPGA resynthesis based on fault-tolerant Boolean matching.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

FPGA area reduction by multi-output function based sequential resynthesis.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Fast dual-vdd buffering based on interconnect prediction and sampling.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Minimal skew clock embedding considering time variant temperature gradient.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Physical Design, 2007

Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2006

An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

DraXRouter: global routing in X-Architecture with dynamic resource assignment.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2005

An-OARSMan: obstacle-avoiding routing tree construction with good length performance.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Via-Aware Global Routing for Good VLSI Manufacturability and High Yield.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Yu Hu

Timeline

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