Yu-Chin Hsu

According to our database, Yu-Chin Hsu authored at least 53 papers between 1987 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Intelligent Chips and Technologies for AIoT Era.

Yu-Chin Hsu, Robert Chen-Hao Chang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2018

Risk assessment in new software development projects at the front end: a fuzzy logic approach.

Ming-Yuan Hsieh, Yu-Chin Hsu, Ching-Torng Lin

J. Ambient Intell. Humaniz. Comput., 2018

2016

Towards Understanding Senior Citizens' Gateball Participations Behavior and Well-Being: An Application of the Theory of Planned Behavior.

Chia-Chien Hsu, Yu-Chin Hsu, Ching-Torng Lin

Proceedings of the Human Interface and the Management of Information: Applications and Services, 2016

2012

Identifying ill tool combinations via Gibbs sampler for semiconductor manufacturing yield diagnosis.

Yu-Chin Hsu, Rong-Huei Chen, Chih-Ming Fan

Proceedings of the Winter Simulation Conference, 2012

2011

A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation.

Gary Miller, Bandana Bhattarai, Yu-Chin Hsu, Jay Dutt, Xi Chen, George Bakewell

Proceedings of the 48th Design Automation Conference, 2011

2008

A General Failure Candidate Ranking Framework for Silicon Debug.

Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

2007

Bridging RTL and gate: correlating different levels of abstraction for design debugging.

Eric Cheung, Xi Chen, Fur-Shing Tsai, Yu-Chin Hsu, Harry Hsieh

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

2006

Diagnosing Silicon Failures Based on Functional Test Patterns.

Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu

Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

Visibility enhancement for silicon debug.

Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang

Proceedings of the 43rd Design Automation Conference, 2006

2003

Advanced techniques for RTL debugging.

Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai

Proceedings of the 40th Design Automation Conference, 2003

2002

Optimal time borrowing analysis and timing budgeting optimization for latch-based designs.

Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai

ACM Trans. Design Autom. Electr. Syst., 2002

2000

Timing optimization on routed designs with incremental placementand routing characterization.

Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1999

Post-routing timing optimization with routing characterization.

Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai

Proceedings of the 1999 International Symposium on Physical Design, 1999

FSMD Functional Partitioning for Low Power.

Enoch Hwang, Frank Vahid, Yu-Chin Hsu

Proceedings of the 1999 Design, 1999

1998

Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance.

Frank Vahid, Thuy Dm Le, Yu-Chin Hsu

ACM Trans. Design Autom. Electr. Syst., 1998

Eliminating false loops caused by sharing in control path.

Alan Su, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee

ACM Trans. Design Autom. Electr. Syst., 1998

1997

Layout Modeling and Design Space Exploration in Pss1 System.

Fur-Shing Tsai, Yu-Chin Hsu

VLSI Design, 1997

Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping.

Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita

Des. Autom. Embed. Syst., 1997

On the control-subroutine implementation of subprogram synthesis.

Cheng-Tsung Hwang, Hsiao-Chien Weng, Yu-Chin Hsu, Mike Tien-Chien Lee

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Cell height driven transistor sizing in a cell based static CMOS module design.

How-Rern Lin, Yu-Chin Hsu, TingTing Hwang

IEEE J. Solid State Circuits, 1996

A Comparison of Functional and Structural Partitioning.

Frank Vahid, Thuy Dm Le, Yu-Chin Hsu

Proceedings of the 9th International Symposium on System Synthesis, 1996

Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL.

Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita

Proceedings of the 33st Conference on Design Automation, 1996

1995

A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits.

Shih-Hsu Huang, Yu-Chin Hsu, Yen-Jen Oyang

Microprocess. Microprogramming, 1995

A new approach to schedule operations across nested-ifs and nested-loops.

Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang

Microprocess. Microprogramming, 1995

Synthesis of false loop free circuits.

Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

MULTIPAR: behavioral partition for synthesizing multiprocessor architectures.

Yunn Yen Chen, Yu-Chin Hsu, Chung-Ta King

IEEE Trans. Very Large Scale Integr. Syst., 1994

Rectilinear Steiner tree construction by local and global refinement.

Ting-Hai Chao, Yu-Chin Hsu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Cell Height Driven Transistor Sizing in a Cell Based Module Design.

How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis.

Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

PLS: a scheduler for pipeline synthesis.

Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Zone scheduling.

Cheng-Tsung Hwang, Yu-Chin Hsu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

High throughput pipelined data path synthesis by conserving the regularity of nested loops.

Yuan-Long Jeang, Yu-Chin Hsu, Jhing-Fa Wang, Jau-Yien Lee

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992

STAR: An automatic data path allocator.

Fur-Shing Tsai, Yu-Chin Hsu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Zero Skew Clock Net Routing.

Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho

Proceedings of the 29th Design Automation Conference, 1992

1991

A formal approach to the scheduling problem in high level synthesis.

Cheng-Tsung Hwang, Jiahn-Humg Lee, Yu-Chin Hsu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

LiB: a CMOS cell compiler.

Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Combining Logic Minimization and Folding for PLA's.

Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, Ting-Hai Chao

IEEE Trans. Computers, 1991

Efficient Microcode Arrangement and Controller Synthesis for Application Specific Integrated Circuits.

Shi-Zheng Lin, Cheng-Tsung Hwang, Yu-Chin Hsu

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation.

Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu

Proceedings of the 28th Design Automation Conference, 1991

Scheduling for Functional Pipelining and Loop Winding.

Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin

Proceedings of the 28th Design Automation Conference, 1991

1990

Hybrid routing.

Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

A fast transistor-chaining algorithm for CMOS cell layout.

Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

A new algorithm for tile generation.

Youn-Long Lin, Yu-Chin Hsu

Integr., 1990

Data Path Construction and Refinement.

Fur-Shing Tsai, Yu-Chin Hsu

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Optimum and Heuristic Data Path Scheduling Under Resource Constraints.

Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Data Path Allocation Based on Bipartite Weighted Matching.

Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

LiB: A Cell Layout Generator.

Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

SILK: a simulated evolution router.

Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Routing using a pyramid data structure.

Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

A new integer linear programming formulation for the scheduling problem in data path synthesis.

Jiahn-Humg Lee, Yu-Chin Hsu, Youn-Long Lin

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

An optimal transistor-chaining algorithm for CMOS cell layout.

Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988

A detailed router based on simulated evolution.

Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987

Floor Planning and Global Routing in an Automated Chip Design System

Yu-Chin Hsu

PhD thesis, 1987