Yu-Chih Tsai

According to our database, Yu-Chih Tsai authored at least 7 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory.

Yun-Chen Lo, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Chih-Chen Yeh, Wen-Chien Ting, Ren-Shuo Liu

IEEE Trans. Computers, September, 2024

2023

LV: Latency-Versatile Floating-Point Engine for High-Performance Deep Neural Networks.

Yun-Chen Lo, Yu-Chih Tsai, Ren-Shuo Liu

IEEE Comput. Archit. Lett., 2023

Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators.

Chia-Chun Wang, Yun-Chen Lo, Jun-Shen Wu, Yu-Chih Tsai, Chia-Cheng Chang, Tsen-Wei Hsu, Min-Wei Chu, Chuan-Yao Lai, Ren-Shuo Liu

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

CNN Inference Accelerators with Adjustable Feature Map Compression Ratios.

Yu-Chih Tsai, Chung-Yueh Liu, Chia-Chun Wang, Tsen-Wei Hsu, Ren-Shuo Liu

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

Built-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for Computing in Memory.

Yu-Chih Tsai, Wen-Chien Ting, Chia-Chun Wang, Chia-Cheng Chang, Ren-Shuo Liu

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators.

Yun-Chen Lo, Chih-Chen Yeh, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Wen-Chien Ting, Ren-Shuo Liu

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2019

A Heart Rate Monitoring and Activities Recognition System for Badminton Training.

Yu-Wen Huang, Shu-Hua Chang, Yu-Chih Tsai, Yuan-Hsiang Lin

Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019