Yu-Chang Tsai

According to our database, Yu-Chang Tsai authored at least 5 papers between 2008 and 2011.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2011

A 0.5-V 0.4-2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip.

Kuo-Hsing Cheng, Yu-Chang Tsai, Yu-Lung Lo, Jing-Shiuan Huang

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010

A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications.

Kuo-Hsing Cheng, Yu-Chang Tsai, Yen-Hsueh Wu, Ying-Fu Lin

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A CMOS adaptive equalizer using low-voltage zero generators technique.

Yu-Chang Tsai, Kuo-Hsing Cheng, Yen-Hsueh Wu, Ying-Fu Lin

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application.

Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Nan Jimmy Liu, Kai-Wei Hong, Chin-Cheng Kuo

IEICE Trans. Electron., 2009

2008

A low jitter self-calibration PLL for 10Gbps SoC transmission links application.

Kuo-Hsing Cheng, Yu-Chang Tsai, Kai-Wei Hong, Yen-Hsueh Wu

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008