Yu Cao
Orcid: 0000-0001-6968-1180Affiliations:
- Arizona State University, School of Electrical, Computer and Energy Engineering, Tempe, AZ, USA
- University of California, Berkeley, CA, USA (PhD 2002)
According to our database1,
Yu Cao
authored at least 221 papers
between 2000 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
IEEE J. Solid State Circuits, July, 2024
ACM Trans. Reconfigurable Technol. Syst., March, 2024
IEEE Trans. Neural Networks Learn. Syst., March, 2024
Uncertainty-Based Extensible Codebook for Discrete Federated Learning in Heterogeneous Data Silos.
CoRR, 2024
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
SpikeSim: An End-to-End Compute-in-Memory Hardware Evaluation Tool for Benchmarking Spiking Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials.
Int. J. High Perform. Comput. Appl., July, 2023
Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA.
ACM Trans. Reconfigurable Technol. Syst., June, 2023
Improving the Efficiency of CMOS Image Sensors through In-Sensor Selective Attention.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A Time-Memory-based CMOS Vision Sensor with In-Pixel Temporal Derivative Computing for Multi-Mode Image Processing.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
Neuromorph. Comput. Eng., December, 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Exploring Model Stability of Deep Neural Networks for Reliable RRAM-Based In-Memory Acceleration.
IEEE Trans. Computers, 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Spatial-temporal Data Compression of Dynamic Vision Sensor Output with High Pixel-level Saliency using Low-precision Sparse Autoencoder.
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022
2021
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks.
ACM Trans. Embed. Comput. Syst., 2021
RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy.
CoRR, 2021
Self-supervised Novelty Detection for Continual Learning: A Gradient-Based Approach Boosted by Binary Classification.
Proceedings of the Continual Semi-Supervised Learning - First International Workshop, 2021
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Proceedings of the International Joint Conference on Neural Networks, 2021
Proceedings of the 20th IEEE International Conference on Machine Learning and Applications, 2021
Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2021
End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
IEEE Des. Test, 2020
Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2020
Proceedings of the International SoC Design Conference, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the Twenty-Ninth International Joint Conference on Artificial Intelligence, 2020
Proceedings of the 19th IEEE International Conference on Machine Learning and Applications, 2020
FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
2019
A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring.
IEEE J. Solid State Circuits, 2019
Guest Editors' Introduction: Hardware and Algorithms for Energy-Constrained On-Chip Machine Learning (Part 2).
ACM J. Emerg. Technol. Comput. Syst., 2019
Guest Editors' Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning.
ACM J. Emerg. Technol. Comput. Syst., 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
CoRR, 2019
Proceedings of the 18th IEEE International Conference On Machine Learning And Applications, 2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition.
ACM J. Emerg. Technol. Comput. Syst., 2018
Guest Editors' Introduction: Frontiers of Hardware and Algorithms for On-chip Learning.
ACM J. Emerg. Technol. Comput. Syst., 2018
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler.
Integr., 2018
CoRR, 2018
Proceedings of the IEEE 1st Conference on Multimedia Information Processing and Retrieval, 2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs.
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Multi Scale Comput. Syst., 2017
ACM J. Emerg. Technol. Comput. Syst., 2017
Neurocomputing, 2017
Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
J. Comput. Sci. Technol., 2016
Optimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniques.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE 16th International Conference on Data Mining, 2016
Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
A Finite-Point Method for Efficient Gate Characterization Under Multiple Input Switching.
ACM Trans. Design Autom. Electr. Syst., 2015
Integr., 2015
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
Programming strategies to improve energy efficiency and reliability of ReRAM memory systems.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Exploiting resistive cross-point array for compact design of physical unclonable function.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell Pram.
J. Signal Process. Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
The Stochastic Loss of Spikes in Spiking Neural P Systems: Design and Implementation of Reliable Arithmetic Circuits.
Fundam. Informaticae, 2014
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
BTI-Induced Aging under Random Stress Waveforms: Modeling, Simulation and Silicon Validation.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
Proceedings of the 5th Annual International Conference on Biologically Inspired Cognitive Architectures, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
ACM J. Emerg. Technol. Comput. Syst., 2013
Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits.
IET Circuits Devices Syst., 2013
Proceedings of the European Solid-State Device Research Conference, 2013
Proceedings of the European Solid-State Device Research Conference, 2013
2012
Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2012
ACM Trans. Design Autom. Electr. Syst., 2012
The potential of Fe-FET for robust design under variations: A compact modeling study.
Microelectron. J., 2012
Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding.
EURASIP J. Adv. Signal Process., 2012
IEEE Des. Test Comput., 2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
An analytical approach to efficient circuit variability analysis in scaled CMOS design.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Integrated Circuits and Systems, Springer, ISBN: 978-1-4614-0445-3, 2011
Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Programmable analog device array (PANDA): a platform for transistor-level analog reconfigurability.
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
2010
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Des. Test Comput., 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 47th Design Automation Conference, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Microelectron. J., 2009
<i>New-Age</i>: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components.
Int. J. Parallel Program., 2009
Found. Trends Electron. Des. Autom., 2009
IEEE Des. Test Comput., 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Proc. IEEE, 2008
Scalable model for predicting the effect of negative bias temperature instability for reliable design.
IET Circuits Devices Syst., 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness.
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
ACM J. Emerg. Technol. Comput. Syst., 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 44th Design Automation Conference, 2007
Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation.
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection.
J. Low Power Electron., 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 43rd Design Automation Conference, 2006
Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Microelectron. J., 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
2003
Improved a priori interconnect predictions and technology extrapolation in the GTX system.
IEEE Trans. Very Large Scale Integr. Syst., 2003
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design.
IEEE J. Solid State Circuits, 2003
IEEE J. Solid State Circuits, 2003
2002
Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion.
IEEE Trans. Very Large Scale Integr. Syst., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Loop-based interconnect modeling and optimization approach for multi-GHz clock network design.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2001
Accurate in situ measurement of peak noise and delay change induced by interconnect coupling.
IEEE J. Solid State Circuits, 2001
Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
2000
Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 37th Conference on Design Automation, 2000
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000