Youxin Gao

According to our database, Youxin Gao authored at least 15 papers between 1997 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2005

IR Drop and Ground Bounce Awareness Timing Model.

Muzhou Shao, Youxin Gao, Li-Pen Yuan, Martin D. F. Wong

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Current Calculation on VLSI Signal Interconnects.

Muzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2003

Maze routing with buffer insertion under transition time constraints.

Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Explicit gate delay model for timing evaluation.

Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee

Proceedings of the 2003 International Symposium on Physical Design, 2003

A fast and accurate method for interconnect current calculation.

Muzhou Shao, D. F. Wong, Youxin Gao, Huijing Cao, Li-Pen Yuan

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Shaping interconnect for uniform current density.

Muzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001

A graph based algorithm for optimal buffer insertion under accurate delay models.

Youxin Gao, D. F. Wong

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

A fast and accurate delay estimation method for buffered interconnects.

Youxin Gao, D. F. Wong

Proceedings of ASP-DAC 2001, 2001

2000

Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model.

Youxin Gao, D. F. Wong

Proceedings of the 2000 Design, 2000

1999

Wire-sizing optimization with inductance consideration using transmission-line model.

Youxin Gao, Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Optimal shape function for a bidirectional wire under Elmore delay model.

Youxin Gao, Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance.

Youxin Gao, D. F. Wong

Integr., 1999

Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model.

Youxin Gao, D. F. Wong

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Shaping a VLSI wire to minimize delay using transmission line model.

Youxin Gao, D. F. Wong

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

Optimal shape function for a bi-directional wire under Elmore delay model.

Youxin Gao, D. F. Wong

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997