Youri Helen

Orcid: 0009-0007-9223-7759

According to our database1, Youri Helen authored at least 9 papers between 2001 and 2024.

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Bibliography

2024
VANDOR: Mitigating SEUs into Quantized Neural Networks.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024

Using High-Level Profiling Data to Early Assess the Robustness of Digital Systems.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024

HTAG-eNN: Hardening Technique with AND Gates for Embedded Neural Networks.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2022
BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Using Application Profiling based on a Virtual Platform for SoC Fault Tolerance Assessment.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

Flodam: Cross-Layer Reliability Analysis Flow for Complex Hardware Designs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
A Region-Based Bit-Shuffling Approach Trading Hardware Cost and Fault Mitigation Efficiency.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020
Multiple Permanent Faults Mitigation Through Bit-Shuffling for Network-an-Chip Architecture.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2001
Improved Stability of Large Area Excimer Laser Crstallised Polysilicon Thin Film Transistors under DC and AC Operating.
Microelectron. Reliab., 2001


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