Youngjoo Lee
Orcid: 0000-0002-2467-8276
According to our database1,
Youngjoo Lee
authored at least 120 papers
between 2007 and 2024.
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Bibliography
2024
Hard-Decision SCL Polar Decoder With Weighted Pruning Operation for Storage Applications.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2024
IEEE Trans. Wirel. Commun., August, 2024
A 43.9 μs IRS Controller SoC With Grid-Based Phase-Shift Optimization in 28 nm CMOS Technology for Next- Generation Communication.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2024
IEEE Wirel. Commun. Lett., March, 2024
CoRR, 2024
16.1 A 2.7-to-13.3μJ/boot/slot Flexible RNS-CKKS Processor in 28nm CMOS Technology for FHE-Based Privacy-Preserving Computing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
LUT-GEMM: Quantized Matrix Multiplication based on LUTs for Efficient Inference in Large-Scale Generative Language Models.
Proceedings of the Twelfth International Conference on Learning Representations, 2024
Partially-Structured Transformer Pruning with Patch-Limited XOR-Gate Compression for Stall-Free Sparse-Model Access.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
Block Orthogonal Sparse Superposition Codes for Ultra-Reliable Low-Latency Communications.
IEEE Trans. Commun., December, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
Simplified Compressor and Encoder Designs for Low-Cost Approximate Radix-4 Booth Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023
A reproducible 3D convolutional neural network with dual attention module (3D-DAM) for Alzheimer's disease classification.
CoRR, 2023
IEEE Access, 2023
IEEE Access, 2023
A 2.35 Gb/s/mm<sup>2</sup> (7440, 6696) NB-LDPC Decoder over GF(32) using Memory-Reduced Column-Wise Trellis Min-Max Algorithm in 28nm CMOS Technology.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Sparsity-Aware Memory Interface Architecture using Stacked XORNet Compression for Accelerating Pruned-DNN Models.
Proceedings of the Sixth Conference on Machine Learning and Systems, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned Transformers.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the 14th International Conference on Information and Communication Technology Convergence, 2023
GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
TF-MVP: Novel Sparsity-Aware Transformer Accelerator with Mixed-Length Vector Pruning.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
IEEE Trans. Veh. Technol., 2022
Area- and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Computers, 2022
IEEE J. Solid State Circuits, 2022
IEEE Commun. Lett., 2022
nuQmm: Quantized MatMul for Efficient Inference of Large-Scale Generative Language Models.
CoRR, 2022
A 1.1μs 1.56Gb/s/mm<sup>2</sup> Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
A 2.86Gb/s Fully-Flexible MU-MIMO Processor for Jointly Optimizing User Selection, Power Allocation, and Precoding in 28nm CMOS Technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC Operator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Novel Mobile Mechanism Design for an Obstacle-Overcoming Robot Using Rotating Spokes.
IEEE Access, 2021
IEEE Access, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Rapid Design Space Exploration of Near-Optimal Memory-Reduced DCNN Architecture Using Multiple Model Compression Techniques.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Conference on Acoustics, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A 7Gbps (160, 80) Non-Binary LDPC Decoder with Dual-Message EMS Algorithm in 22nm FinFET Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
Energy-Efficient Intelligent EPTS Device using Novel DCNN-Based Dynamic Sensor Activation.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
Utilizing Energy-Quality Trade-Off for Low-Cost ML-Based Compressive Sensing Reconstruction.
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Energy-Efficient Wearable EPTS Device Using On-Device DCNN Processing for Football Activity Classification.
Sensors, 2020
IEEE Robotics Autom. Lett., 2020
Low-Complexity DNN-Based End-to-End Automatic Speech Recognition using Low-Rank Approximation.
Proceedings of the International SoC Design Conference, 2020
Proceedings of the International SoC Design Conference, 2020
Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020
2019
Rapid Balise Telegram Decoder With Modified LFSR Architecture for Train Protection Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Memory-Reduced Network Stacking for Edge-Level CNN Architecture With Structured Weight Pruning.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Massive MIMO Systems With Low-Resolution ADCs: Baseband Energy Consumption vs. Symbol Detection Performance.
IEEE Access, 2019
Selective Deep Convolutional Neural Network for Low Cost Distorted Image Classification.
IEEE Access, 2019
Design of a Low-Power BLE5-Based Wearable Device for Tracking Movements of Football Players.
Proceedings of the 2019 International SoC Design Conference, 2019
WMixNet: An Energy-Scalable and Computationally Lightweight Deep Learning Accelerator.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Similarity-Based LSTM Architecture for Energy-Efficient Edge-Level Speech Recognition.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Ultra-Low-Latency Parallel SC Polar Decoding Architecture for 5G Wireless Communications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Low-Complexity Dynamic Channel Scaling of Noise-Resilient CNN for Intelligent Edge Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
FPGA-Based Sparsity-Aware CNN Accelerator for Noise-Resilient Edge-Level Image Recognition.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
IEEE Access, 2018
Data Transfusion: Pairing Wearable Devices and Its Implication on Security for Internet of Things.
IEEE Access, 2018
Fixed-Point Quantization of 3D Convolutional Neural Networks for Energy-Efficient Action Recognition.
Proceedings of the International SoC Design Conference, 2018
Proceedings of the International SoC Design Conference, 2018
A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Proceedings of the International SoC Design Conference, 2017
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017
An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEICE Trans. Electron., 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the Neural Information Processing - 23rd International Conference, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Binary tree optimization using genetic algorithm for multiclass support vector machine.
Expert Syst. Appl., 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory.
IEEE J. Solid State Circuits, 2013
Inf. Syst. Frontiers, 2013
Corrigendum to "Fast and efficient lung disease classification using hierarchical one-against-all support vector machine and cost-sensitive feature selection" [Comput. Biol. Med 42 (2012) 1157-1164].
Comput. Biol. Medicine, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Fast and efficient lung disease classification using hierarchical one-against-all support vector machine and cost-sensitive feature selection.
Comput. Biol. Medicine, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Regional Context-Sensitive Support Vector Machine Classifier to Improve Automated Identification of Regional Patterns of Diffuse Interstitial Lung Disease.
J. Digit. Imaging, 2011
Statistical modeling of capacitor mismatch effects for successive approximation register ADCs.
Proceedings of the International SoC Design Conference, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
Development of an Automatic Classification System for Differentiation of Obstructive Lung Disease using HRCT.
J. Digit. Imaging, 2009
Performance testing of several classifiers for differentiating obstructive lung diseases based on texture analysis at high-resolution computerized tomography (HRCT).
Comput. Methods Programs Biomed., 2009
Improvement of computational efficiency using a cascade classification scheme for the classification of diffuse infiltrative lung disease on HRCT.
Proceedings of the Medical Imaging 2009: Computer-Aided Diagnosis, 2009
A computer-aided differential diagnosis between UIP and NSIP using automated assessment of the extent and distribution of regional disease patterns at HRCT: comparison with the radiologist's decision.
Proceedings of the Medical Imaging 2009: Computer-Aided Diagnosis, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Effect of various binning methods and ROI sizes on the accuracy of the automatic classification system for differentiation between diffuse infiltrative lung diseases on the basis of texture features at HRCT.
Proceedings of the Medical Imaging 2008: Image Processing, 2008
2007
Performance comparison of classifiers for differentiation among obstructive lung diseases based on features of texture analysis at HRCT.
Proceedings of the Medical Imaging 2007: Image Processing, 2007
The performance improvement of automatic classification among obstructive lung diseases on the basis of the features of shape analysis, in addition to texture analysis at HRCT.
Proceedings of the Medical Imaging 2007: Image Processing, 2007