Youngil Lim
Orcid: 0000-0002-5773-0296
According to our database1,
Youngil Lim
authored at least 3 papers
between 2005 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2021
An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques.
IEEE J. Solid State Circuits, 2021
2020
22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2005
Proceedings of the Virtual Storytelling, 2005