Younghoon Byun

Orcid: 0000-0003-1899-6259

Affiliations:
  • Pohang University of Science and Technology, South Korea


According to our database1, Younghoon Byun authored at least 13 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2024
Partially-Structured Transformer Pruning with Patch-Limited XOR-Gate Compression for Stall-Free Sparse-Model Access.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Sparsity-Aware Memory Interface Architecture using Stacked XORNet Compression for Accelerating Pruned-DNN Models.
Proceedings of the Sixth Conference on Machine Learning and Systems, 2023

Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned Transformers.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

2022
CHAMP: Channel Merging Process for Cost-Efficient Highly-Pruned CNN Acceleration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021
Layerwise Buffer Voltage Scaling for Energy-Efficient Convolutional Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Rapid Design Space Exploration of Near-Optimal Memory-Reduced DCNN Architecture Using Multiple Model Compression Techniques.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Approach to Improve the Performance Using Bit-level Sparsity in Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2019
Memory-Reduced Network Stacking for Edge-Level CNN Architecture With Structured Weight Pruning.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Selective Deep Convolutional Neural Network for Low Cost Distorted Image Classification.
IEEE Access, 2019

Low-Complexity Dynamic Channel Scaling of Noise-Resilient CNN for Intelligent Edge Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

FPGA-Based Sparsity-Aware CNN Accelerator for Noise-Resilient Edge-Level Image Recognition.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

Multi-level Weight Indexing Scheme for Memory-Reduced Convolutional Neural Network.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
Fixed-Point Quantization of 3D Convolutional Neural Networks for Energy-Efficient Action Recognition.
Proceedings of the International SoC Design Conference, 2018


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