Young-Su Kwon

According to our database1, Young-Su Kwon authored at least 45 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Multi-Stripline Redistribution Layer Interposer Channel Design for High Bandwidth Memory Module Considering Via Interconnect.
Proceedings of the 20th International SoC Design Conference, 2023

DQ and DQS Receiver for HBM3 Memory Interface with DFE Offset Calibration.
Proceedings of the 20th International SoC Design Conference, 2023

ABSX: The Chiplet Hyperscale AI Processing Unit for Energy-Efficient High-Performance AI Processing.
Proceedings of the 20th International SoC Design Conference, 2023

2.5D Large-Scale Interposer Bonding Process Verification using Daisy-Chain for PIM Heterogeneous Integration Platform.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023

Chiplet Heterogeneous-Integration AI Processor.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023

2022
Backward Graph Construction and Lowering in DL Compiler for Model Training on AI Accelerators.
Proceedings of the 19th International SoC Design Conference, 2022

AIWareK: Compiling PyTorch Model for AI Processor Using MLIR Framework.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

M3FPU: Multiformat Matrix Multiplication FPU Architectures for Neural Network Computations.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

ArtBrain-K: AI Processor based-on 5-PetaFLOPS AI Server System.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Live Demonstration: A Neural Processor for AI Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

HPC LINPACK Parameter Optimization on Homo-/Heterogeneous System of ARM Neoverse N1SDP.
Proceedings of the HPC Asia 2021: The International Conference on High Performance Computing in Asia-Pacific Region, 2021

2019
AI 32TFLOPS Autonomous Driving Processor on AI-Ware with Adaptive Power Saving.
Proceedings of the 2019 International SoC Design Conference, 2019

Implementation of Yolo-v2 Image Recognition and Other Testbenches for a CNN Accelerator.
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019

Function-Safe Vehicular AI Processor with Nano Core-In-Memory Architecture.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2017
A deep learning convolution architecture for simple embedded applications.
Proceedings of the 7th IEEE International Conference on Consumer Electronics - Berlin, 2017

A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A Fault-Tolerant Cache System of Automotive Vision Processor Complying With ISO26262.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

2010
Partial access conflict-relieving programmable address shuffler for parallel memory system in multi-core processor.
Microprocess. Microsystems, 2010

Application-Adaptive Reconfiguration of Memory Address Shuffler for FPGA-Embedded Instruction-Set Processor.
J. Circuits Syst. Comput., 2010

Transparent session transfer in converged IP Messaging systems.
Proceedings of the 2010 Wireless Telecommunications Symposium, 2010

2009
Implmentation of digital audio effect SoC.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

Partial conflict-relieving programmable address shuffler for parallel memories in multi-core processor.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Standstill Parameter Identification of Vector-Controlled Induction Motor Using Frequency Characteristics of Rotor Bars.
Proceedings of the Industry Applications Society Annual Meeting, 2008

Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor.
Proceedings of the FPL 2008, 2008

A 159.2mW SoC implementation of T-DMB receiver including stacked memories.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2005
ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool.
Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005

Simulation acceleration of transaction-level models for SoC with RTL sub-blocks.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture.
Microprocess. Microsystems, 2004

Functional Coverage Metric Generation from Temporal Event Relation Graph.
Proceedings of the 2004 Design, 2004

Systematic functional coverage metric synthesis from hierarchical temporal event relation graph.
Proceedings of the 41th Design Automation Conference, 2004

Communication-efficient hardware acceleration for fast functional simulation.
Proceedings of the 41th Design Automation Conference, 2004

Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection.
Proceedings of the IFIP VLSI-SoC 2003, 2003

SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2000
MetaCore: an application-specific programmable DSP development system.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Pyramid Texture Compression and Decompression Using Interpolative Vector Quantization.
Proceedings of the 2000 International Conference on Image Processing, 2000

FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

Fast development of source-level debugging system using hardware emulation (short paper).
Proceedings of ASP-DAC 2000, 2000

A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics.
Proceedings of ASP-DAC 2000, 2000

1999
DIVA: dual-issue VLIW architecture with media instructions for image processing.
IEEE Trans. Consumer Electron., 1999

MDSP-II: a 16-bit DSP with mobile communication accelerator.
IEEE J. Solid State Circuits, 1999

A New Single-Clock Flip-Clop for Half-Swing Clocking.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998


  Loading...