Young-Kyun Cho

According to our database, Young-Kyun Cho authored at least 15 papers between 2009 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Quasi-Resonant Fly-Buck Converter With Active Switching for Improved Output Voltage Boosting and Regulation.

Gyeong-Seop Lim, Wi-Min Kim, Young-Kyun Cho, Sang-Won Lee

IEEE Trans. Ind. Electron., October, 2024

A Dual-Mode Continuous-Time Sigma-Delta Modulator With a Reconfigurable Loop Filter Based on a Single Op-Amp Resonator.

Young-Kyun Cho

IEEE Trans. Very Large Scale Integr. Syst., September, 2024

A Single Op-Amp Resonator-Based Continuous-Time Sigma-Delta Modulator With Time-Division Switching for Excess Loop Delay Compensation.

Young-Kyun Cho

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

A Compact Slotted Waveguide Array Antenna With a Cubic Post Radiator for Aerial Vehicle Applications.

Ka-Hyeon Lee, Su-Jeong Yun, Jeong-Nam Lee, Young-Kyun Cho

IEEE Access, 2024

2023

Compact size buck converter using small output capacitance with pole-tuning technique.

Jae-Eun Lee, Young-Kyun Cho, Choul-Young Kim

Microelectron. J., 2023

2022

A Low-Power Class-C Voltage-Controlled Oscillator With Robust Start-Up and Compact High-Q Capacitor Array.

Young-Kyun Cho, Jae-Won Nam, Sang-Won Lee

IEEE Trans. Circuits Syst. II Express Briefs, 2022

2018

A Low-Power Continuous-Time Delta-Sigma Modulator Using a Resonant Single Op-Amp Third-Order Loop Filter.

Young-Kyun Cho, Myung-Don Kim, Choul-Young Kim

IEEE Trans. Circuits Syst. II Express Briefs, 2018

2015

Compensation technique for time alignment of envelope and phase paths in an envelope delta-sigma modulator.

Sung Jun Lee, Young-Kyun Cho, Jae Ho Jung

IEICE Electron. Express, 2015

2012

20-MHz bandwidth continuous-time delta-sigma modulator for EPWM transmitter.

Young-Kyun Cho, Sung Jun Lee, Seung Hyun Jang, Bong Hyuk Park, Jae Ho Jung, Kwang Chun Lee

Proceedings of the 2012 International Symposium on Wireless Communication Systems (ISWCS), 2012

A 9-bit 100-MS/s flash-SAR ADC without track-and-hold circuits.

Young-Kyun Cho, Jae Ho Jung, Kwang Chun Lee

Proceedings of the 2012 International Symposium on Wireless Communication Systems (ISWCS), 2012

2011

A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique.

Jae-Won Nam, Young-Deuk Jeon, Young-Kyun Cho, Jong-Kee Kwon

Microelectron. J., 2011

A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications.

Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon

Microelectron. J., 2011

2010

A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique.

Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 9.15mW 0.22mm² 10b 204MS/s pipelined SAR ADC in 65nm CMOS.

Young-Deuk Jeon, Young-Kyun Cho, Jae-Won Nam, Kwi-Dong Kim, Woo-Yol Lee, Kuk-Tae Hong, Jong-Kee Kwon

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS.

Jae-Won Nam, Young-Deuk Jeon, Young-Kyun Cho, Sang-Gug Lee, Jong-Kee Kwon

Proceedings of the 35th European Solid-State Circuits Conference, 2009