Young-Jung Choi
According to our database1,
Young-Jung Choi
authored at least 19 papers
between 2006 and 2013.
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Bibliography
2013
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology.
IEEE J. Solid State Circuits, 2012
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces.
IEEE J. Solid State Circuits, 2012
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEICE Electron. Express, 2009
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the International Conference on Embedded Software and Systems, 2008
A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme.
Proceedings of the ESSCIRC 2008, 2008
2007
A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL.
IEEE J. Solid State Circuits, 2007
A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006