Young Choi
Orcid: 0000-0002-0608-0166
According to our database1,
Young Choi
authored at least 24 papers
between 2001 and 2024.
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Bibliography
2024
A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024
Crack Detection and Analysis of Concrete Structures Based on Neural Network and Clustering.
Sensors, March, 2024
2023
Characterization and design of two-dimensional multi-morphology cellular structures for desired deformation.
J. Comput. Des. Eng., March, 2023
2022
A Stacked Generalization Model to Enhance Prediction of Earthquake-Induced Soil Liquefaction.
Sensors, 2022
2021
Implicit-based computer-aided design for additively manufactured functionally graded cellular structures.
J. Comput. Des. Eng., 2021
J. Comput. Des. Eng., 2021
2020
Concurrent density distribution and build orientation optimization of additively manufactured functionally graded lattice structures.
Comput. Aided Des., 2020
2019
Triangular Mesh and Boundary Representation Combined Approach for 3D CAD Lightweight Representation for Collaborative Product Development.
J. Comput. Inf. Sci. Eng., 2019
Tangible interface for shape modeling by block assembly of wirelessly connected blocks.
J. Comput. Des. Eng., 2019
2018
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
Reconstruction of Intima and Adventitia Models into a State Undeformed by a Catheter by Using CT, IVUS, and Biplane X-Ray Angiogram Images.
Comput. Math. Methods Medicine, 2017
23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2013
A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme.
IEEE J. Solid State Circuits, 2013
2012
A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2010
Triangulation of CAD data for visualization using a compact array-based triangle data structure.
Comput. Graph., 2010
2009
Comparison of decentralized time slot allocation strategies for asymmetric traffic in TDD systems.
IEEE Trans. Wirel. Commun., 2009
A modified advancing layers mesh generation for thin three-dimensional objects with variable thickness.
Comput. Graph., 2009
CAD data visualization on mobile devices using sequential constrained Delaunay triangulation.
Comput. Aided Des., 2009
2007
Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007
Proceedings of the Computational Science and Its Applications, 2007
2006
A Zone-Based Clustering Method for Ubiquitous Robots Based on Wireless Sensor Networks.
Proceedings of the Smart Sensing and Context, First European Conference, EuroSSC 2006, 2006
2003
Finite element analysis with STEP in distributed and concurrent engineering environment.
Proceedings of the Enhanced Interoperable Systems. Proceedings of the 10th ISPE International Conference on Concurrent Engineering (ISPE CE 2003), 2003
2002
Concurr. Eng. Res. Appl., 2002
2001
Proceedings of the 30th International Workshops on Parallel Processing (ICPP 2001 Workshops), 2001