Youji Idei

According to our database, Youji Idei authored at least 3 papers between 1995 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1998

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register.

Youji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Hidetoshi Iwai, Katsuyuki Sato, Tadashi Tachibana

IEEE J. Solid State Circuits, 1998

1996

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry.

Keiichi Higeta, Masami Usami, Masayuki Ohayashi, Yasuhiro Fujimura, Masahiko Nishiyama, Satoru Isomura, Kunihiko Yamaguchi, Youji Idei, Hiroaki Nambu, Kenichi Ohhata, Nadateru Hanta

IEEE J. Solid State Circuits, 1996

1995

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM.

Hiroalu Nambu, Kazuo Kanetani, Youji Idei, Tom Masuda, Keiichi Higeta, Masayuki Ohayashi, Masami Usami, Kunihiko Yamaguchi, Toshiyuki Kikuchi, Takahide Ikeda, Kenichi Ohhata, Takeshi Kusunoki, Noriyuki Homma

IEEE J. Solid State Circuits, April, 1995