Youhua Shi

According to our database, Youhua Shi authored at least 59 papers between 2003 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Strategy for Improving Cycle of Maximized Energy Output of Triboelectric Nanogenerators.

Yirui Su, Masao Yanagisawa, Youhua Shi

Proceedings of the International Conference on IC Design and Technology, 2023

An Area-Power-Efficient Multiplier-less Processing Element Design for CNN Accelerators.

Jiaxiang Li, Masao Yanagisawa, Youhua Shi

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2021

Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow.

Lin Ye, Jinghao Ye, Masao Yanagisawa, Youhua Shi

IEEE Access, 2021

A Reconfigurable Area and Energy Efficient Hardware Accelerator of Five High-order Operators for Vision Sensor Based Robot Systems.

Qianjin Wang, Yi Zhan, Bingqiang Liu, Jiajun Wu, Youhua Shi, Guoyi Yu, Chao Wang

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

2020

Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets.

Saki Tajima, Masao Yanagisawa, Youhua Shi

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy.

Jinghao Ye, Masao Yanagisawa, Youhua Shi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filters.

Jinghao Ye, Masao Yanagisawa, Youhua Shi

Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019

Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs.

Jinghao Ye, Nozomu Togawa, Masao Yanagisawa, Youhua Shi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

An Adder-Segmentation-based FIR for High Speed Signal Processing.

Jinghao Ye, Masao Yanagisawa, Youhua Shi

Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Zero-Gating Processing Element Design for Low-Power Deep Convolutional Neural Networks.

Lin Ye, Jinghao Ye, Masao Yanagisawa, Youhua Shi

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing.

Jinghao Ye, Masao Yanagisawa, Youhua Shi

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018

A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element.

Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs.

Ken Hayamizu, Nozomu Togawa, Masao Yanagisawa, Youhua Shi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Hardware Trojan Detection Utilizing Machine Learning Approaches.

Kento Hasegawa, Youhua Shi, Nozomu Togawa

Proceedings of the 17th IEEE International Conference On Trust, 2018

2017

A low cost and high speed CSD-based symmetric transpose block FIR implementation.

Jinghao Ye, Youhua Shi, Nozomu Togawa, Masao Yanagisawa

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Soft error tolerant latch designs with low power consumption (invited paper).

Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Timing monitoring paths selection for wide voltage IC.

Weiwei Shan, Wentao Dai, Youhua Shi, Peng Cao, Xiaoyan Xiang

IEICE Electron. Express, 2016

In-situ Trojan authentication for invalidating hardware-Trojan functions.

Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

A delay variation and floorplan aware high-level synthesis algorithm with body biasing.

Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015

An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead.

Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists.

Masaru Oya, Youhua Shi, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Satoshi Goto, Masao Yanagisawa, Nozomu Togawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design.

Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures.

Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A score-based classification method for identifying hardware-trojans at gate-level netlists.

Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation.

Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A low-power soft error tolerant latch scheme.

Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

Throughput driven check point selection in suspicious timing error prediction based designs.

Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction.

Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

In-situ timing monitoring methods for variation-resilient designs.

Youhua Shi, Nozomu Togawa

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Secure scan design using improved random order and its evaluations.

Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages.

Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages.

Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Secure Scan Design with Dynamically Configurable Connection.

Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

Suspicious timing error prediction with in-cycle clock gating.

Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, Masao Yanagisawa

Proceedings of the International Symposium on Quality Electronic Design, 2013

Concurrent faulty clock detection for crypto circuits against clock glitch based DFA.

Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEEE Trans. Very Large Scale Integr. Syst., 2012

Scan-Based Attack on AES through Round Registers and Its Countermeasure.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

MH⁴ : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures.

Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

IEICE Electron. Express, 2012

Dynamically changeable secure scan architecture against scan-based side channel attack.

Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

Proceedings of the International SoC Design Conference, 2012

State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit.

Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2010

Improved Launch for Higher TDF Coverage With Fewer Test Patterns.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

State-dependent changeable scan architecture against scan-based side channel attacks.

Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding.

Youhua Shi, Kenta Tokumitsu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in <i>GF</i>(<i>P</i>) and <i>GF</i>(2^<i>n</i>).

Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Design-for-secure-test for crypto cores.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2009 IEEE International Test Conference, 2009

2008

A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A Secure Test Technique for Pipelined Advanced Encryption Standard.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Inf. Syst., 2008

Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2ⁿ).

Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

GECOM: Test data compression combined with all unknown response masking.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Unknown response masking with minimized observable response loss and mask data.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains.

Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters.

Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

FCSCAN: an efficient multiscan-based test compression technique for test cost reduction.

Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Low Power Test Compression Technique for Designs with Multiple Scan Chain.

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test.

Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation.

Youhua Shi, Zhe Zhang, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Multiple test set generation method for LFSR-based BIST.

Youhua Shi, Zhe Zhang

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003