You Wang
Orcid: 0000-0003-3409-161XAffiliations:
- Beihang University, Hefei Innovation Research Institute, Hefei, China
- Beihang Univeristy, School of Electronic and Information Engineering, Fert Beijing Institute, Beijing, China
- Télécom ParisTech, Institut Mines-Télécom, Paris, France (PhD 2017)
According to our database1,
You Wang
authored at least 41 papers
between 2014 and 2024.
Collaborative distances:
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Bibliography
2024
A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
2023
A Novel 9T1C-SRAM Compute-In-Memory Macro With Count-Less Pulse-Width Modulation Input and ADC-Less Charge-Integration-Count Output.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
2022
A Machine Learning Attack-Resilient Strong PUF Leveraging the Process Variation of MRAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Reconfigurable and Dynamically Transformable In-Cache-MPUF System With True Randomness Based on the SOT-MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022
Proceedings of the Approximate Computing, 2022
2021
A Novel Multi-Context Non-Volatile Content-Addressable Memory Cell and Multi-Level Architecture for High Reliability and Density.
Proceedings of the 10th IEEE Non-Volatile Memory Systems and Applications Symposium, 2021
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
Fully Single Event Double Node Upset Tolerant Design for Magnetic Random Access Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
SpinSim: A Computer Architecture-Level Variation Aware STT-MRAM Performance Evaluation Framework.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Radiation Hardened Design of STT-MRAM with High Recoverability from Double Node Upset.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
2020
Compact Modeling and Analysis of Voltage-Gated Spin-Orbit Torque Magnetic Tunnel Junction.
IEEE Access, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
2018
Microelectron. J., 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
2016
A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI.
Microelectron. Reliab., 2016
Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters.
Microelectron. Reliab., 2016
Microelectron. Reliab., 2016
A novel circuit design of true random number generator using magnetic tunnel junction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
2015
Microelectron. Reliab., 2015
Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology.
Microelectron. Reliab., 2015
Cross-layer investigation of continuous-time sigma-delta modulator under aging effects.
Microelectron. Reliab., 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
2014
Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses.
Microelectron. Reliab., 2014